Asic Design Engineer Jobs

About The Position

Requirements

• Ability to obtain a U.S. Security Clearance; U.S. citizenship is required, with an interim and/or final U.S. Secret Clearance required post-start.
• Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical, or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry, or directly related non-U.S. equivalent qualifications.
• Bachelor’s degree and 9 or more years of FPGA, ASIC, or SoC digital design experience; alternatively, a BS/MS and 7 or more years of FPGA, ASIC, or SoC digital design experience.
• Experience with HDL development, simulation, debugging, and synthesis.
• Strong digital design fundamentals, including projects involving digital logic design or computer architecture.
• Experience troubleshooting digital systems, including RTL design, HDL, or architecture debugging.
• Understanding of timing fundamentals and CDC concepts.
• Successful completion of the company’s Conflict of Interest assessment process.

Nice To Haves

• For Senior Level 5, 14 or more years of related engineering experience.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Requirements development and traceability experience.
• FPGA implementation experience, including constraints and timing closure.
• Static timing analysis experience.
• Verification collaboration experience.
• Experience with high-speed interfaces, processor integration, memory subsystems, or SoC integration.
• Mentoring or technical leadership exposure.
• Familiarity with industry-standard tools and methodologies.
• ABET-accredited education is preferred in the United States, but not required.

Responsibilities

• Support ASIC, FPGA, or mixed ASIC/FPGA developments according to assignment.
• Contribute to requirements development and refinement, interface definition, conceptual architecture activities, and traceability appropriate to role level.
• Develop HDL/RTL for ASIC, FPGA, and SoC systems.
• Compile, simulate, debug, and troubleshoot digital designs.
• Perform or support synthesis, implementation, constraints development, timing closure, and tool execution.
• Collaborate with verification teams to support simulation, debugging, coverage, and integration goals.
• Apply timing concepts, CDC fundamentals, and integration considerations.
• Support broader system troubleshooting and integration activities.
• Communicate technical status, risks, dependencies, and tradeoffs proactively.
• Manage assigned scope and execution with ownership appropriate to role level.
• Develop technical breadth while deepening selected expertise, support peer development and technical collaboration, and build systems awareness beyond immediate design boundaries.
• For Lead Level 4: support subsystem ownership, mentor others, and lead larger technical efforts, integration activities, or technical teams.
• For Senior Level 5: provide technical leadership, support architecture direction and broader technical ownership, and lead teams, subsystem efforts, and cross-functional initiatives.

Benefits

• Eligible employees may enroll in health insurance, flexible spending accounts, health savings accounts, retirement savings plans, life and disability insurance programs, and programs providing paid and unpaid time away from work.
• Competitive base pay and variable compensation opportunities.
• Relocation may be offered based on candidate eligibility; basic relocation is offered for eligible internal candidates.