Principal ASIC DFT Design Engineer - Terawave
About The Position
Blue Origin is developing TeraWave, a satellite communications network designed to provide symmetrical data speeds of up to 6 Tbps worldwide for enterprise, data center, and government users. As a Principal ASIC DFT Designer on the ASIC Engineering SOC Team, you will own design-for-test architecture for the TeraWave System on Chip (SOC) program. You will define test strategy for large multi-block SOC designs, implement scan, compression, and built-in self-test infrastructure, and deliver test vectors to qualify silicon on automated test equipment. This is a senior individual-contributor position with technical leadership scope and no direct reports. The work spans specification through silicon bring-up, including ATE pattern debugging and support for defect and yield analysis, and is directly relevant to test quality and manufacturability. Applicants must be a U.S. citizen or national, U.S. permanent resident, or lawfully admitted to the U.S. as a refugee or granted asylum. A standard background check is required; additional checks may apply to certain job profiles.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
- At least 10 years of experience in design for test for complex digital SOCs.
- Experience defining DFT architecture and specifications for large multi-block SOC designs.
- Experience with DC and AC scan design and memory built-in self-test implementation.
- Experience generating ATPG patterns for automated test equipment and debugging ATE patterns.
- Must be a U.S. citizen or national, U.S. permanent resident, or lawfully admitted into the U.S. as a refugee or granted asylum.
Nice To Haves
- Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.
- Experience with logic built-in self-test implementation and signature-based test methodologies.
- Experience with defect analysis and yield improvement for advanced process-node silicon.
- Experience with hierarchical DFT and IEEE 1500 or IEEE 1687 test access standards.
- Experience with commercial DFT tool flows such as Tessent, DFTMAX, or Modus.
- Experience reducing test time and test cost through pattern and compression optimization.
- Strong written and verbal communication skills for presenting test strategy to technical stakeholders.
Responsibilities
- Define DFT architecture and test strategy for large multi-block SOC designs.
- Author DFT specifications covering scan, compression, boundary scan, and test access mechanisms.
- Implement scan-chain insertion, test-clock control, and on-chip compression logic.
- Design memory and logic built-in self-test infrastructure for embedded memories and logic.
- Generate and validate DFT vectors for silicon bring-up and production test programs.
- Debug ATE pattern failures and drive resolution with design and product engineering teams.
- Support defect analysis and yield improvement using test coverage and silicon failure data.
- Review test coverage and DFT timing metrics with physical design and verification teams.
Benefits
- Medical, dental, and vision insurance.
- Basic and supplemental life insurance.
- Paid parental leave.
- Short- and long-term disability.
- 401(k) with a company match of up to 5%.
- Education Support Program.
- Stock options for regular employees working at least 20 hours per week.
- Paid time off of up to four weeks per year based on weekly scheduled hours.
- Up to 14 company-paid holidays.
- Depending on role type and job level, employees may be eligible for benefits and bonuses based on individual contributions, company results, or other factors; amounts and eligibility are not guaranteed.
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What This Job Offers
Job Type
Full-time
Career Level
Principal
