Senior ASIC Design Verification Engineer - Terawave

Blue Origin • Hutto, TX

4h

About The Position

Blue Origin is pioneering TeraWave, a multi-orbit satellite communications network designed to provide symmetrical data speeds of up to 6 Tbps worldwide through optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO). The ASIC Verification Engineer leads verification of complex digital subsystems for next-generation satellite communications ASICs. The role calls for advanced verification expertise, architectural understanding, and collaboration across functions to ensure robust, high-quality silicon.

The position leads verification planning and execution for complex blocks or subsystems, develops sophisticated UVM environments and related verification assets, and translates architecture and design specifications into strategies with measurable coverage goals. It drives coverage closure, regression health, and signoff readiness; identifies verification gaps and high-risk scenarios; and collaborates with design, systems, DFT, firmware, and physical design teams. The engineer also reviews verification approaches, mentors junior engineers, and supports bring-up, emulation, prototyping, and post-silicon debug as needed.

Requirements

• BS or MS in Electrical Engineering, Computer Engineering, or a related field.
• 8+ years of ASIC/SoC verification experience.
• Deep hands-on expertise in SystemVerilog and UVM.
• Strong understanding of verification planning, assertions, and coverage closure.
• Experience verifying complex digital control and datapath logic.
• Proven debugging capability across RTL, testbench, and system interactions.
• Ability to work effectively across multidisciplinary engineering teams.

Nice To Haves

• Background in space-based communications, wireless communications, or modem/baseband hardware.
• Experience verifying LDPC/BCH/FEC blocks, framing engines, beamforming logic, or DSP pipelines.
• Familiarity with formal verification tools and methodologies.
• Experience with low-power verification, CDC/RDC verification, or reset-domain behavior.
• Knowledge of high-speed interface verification and hardware/software interactions.

Responsibilities

• Lead verification planning and execution for complex blocks or subsystems.
• Develop UVM environments, reference models, scoreboards, protocol monitors, and assertions.
• Translate architecture and design specifications into comprehensive verification strategies and measurable coverage goals.
• Drive functional coverage closure, regression health, and verification signoff readiness.
• Identify verification gaps, corner cases, and high-risk scenarios early in development.
• Collaborate with design, systems, DFT, firmware, and physical design teams.
• Review testbench architecture, stimulus quality, and debug methodologies.
• Mentor junior engineers in verification standard processes.
• Support bring-up, emulation, prototyping, and post-silicon debug activities as needed.

Benefits

• Medical, dental, and vision insurance.
• Basic and supplemental life insurance.
• Paid parental leave.
• Short- and long-term disability.
• 401(k) with company match of up to 5%.
• Education Support Program.
• Stock options for regular employees working at least 20 hours per week.
• Up to four weeks of paid time off per year based on weekly scheduled hours.
• Up to 14 company-paid holidays.
• Employees may be eligible for benefits and bonuses based on role type, job level, individual contributions, company results, or other factors; amounts and eligibility are not guaranteed.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior