ASIC Design Verification Engineer

Ericsson • Austin, TX

19h • Hybrid

About The Position

Ericsson is seeking an ASIC Design Verification Engineer to join its ASIC IP organization in Austin, Texas. The role contributes to verification of ASICs used in production 5G infrastructure and involves ownership across the verification stack, from early architectural verification through block- and top-level verification. The engineer will develop transaction-level models, build UVM testbench environments, close coverage, and perform software-driven verification connecting hardware with embedded software. This is a hands-on role focused on building verification infrastructure and finding important design bugs.

Requirements

• Several years of hands-on, industry RTL verification experience in IP, ASIC, or SoC.
• Deep practical experience with SystemVerilog and UVM.
• Proven ability to architect and build testbenches from the ground up.
• Block- and/or top-level RTL debug experience.
• Familiarity with one or more of SerDes, PCIe, ARM subsystems, DSPs/accelerators, or Ethernet.
• Scripting proficiency in TCL, Python, Perl, or an equivalent language.
• Clear, confident communication skills.
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent hands-on experience.

Nice To Haves

• Experience developing full test plans and directed or randomized test cases from scratch.
• Object-oriented programming skills applied to verification code.
• Embedded software design and test experience.
• Fluency in the standard Linux/GIT/LSF development environment.
• Hands-on experience with AMBA APB, AXI, ACE-Lite, or CHI interfaces.
• Familiarity with computer architecture, including CPU pipelines, memory hierarchies, and cache coherency protocols.
• Early leadership instincts and interest in developing leadership skills.

Responsibilities

• Build transaction-level models for early architectural verification.
• Own block- and top-level ASIC/IP verification and coverage closure.
• Design and build UVM testbench environments from the ground up.
• Perform software-driven verification that connects hardware and embedded software to verify real-world behavior.
• Debug RTL and identify design bugs.

Benefits

• Annual bonus opportunity through the Short-Term Variable Compensation Plan, subject to eligibility and payout rules.
• Choice of three medical plan options and a dental plan option.
• 401(k) plan with automatic company contributions and matching contributions.
• Basic life insurance and accidental death and dismemberment coverage.
• Short-term and long-term disability coverage.
• Option to participate in the Stock Purchase Plan.
• Minimum of 15 accrued vacation days, up to 3 personal days per year, 11 annual holidays, 8 hours of volunteer time, and 80 hours of sick time annually.
• Up to 16 weeks of paid maternity leave and 6 weeks of parental or adoption leave at 100% of pay.
• Financial wellness programs, educational assistance, matching gifts, and recognition programs.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level