Principal ASIC Design

Fortinet • Sunnyvale, CA

2d

About The Position

Fortinet is seeking an ASIC Designer to join its R&D team and help architect and design next-generation FortiASIC technology for high-performance network security systems. The role spans the ASIC design lifecycle, from initial specifications and architecture through RTL implementation, verification, and chip-level delivery. The designer will contribute to AI-powered network-processing ASIC architecture, IP integration, and chip-level RTL design and verification, while working with cross-functional engineering teams.

Requirements

• At least 8 years of experience in high-performance networking or processor design.
• Proven experience taking complex ASIC or FPGA designs from initial concept to mass production.
• Hands-on expertise in Verilog or SystemVerilog HDL coding, synthesis, and design verification.
• In-depth experience across the high-performance ASIC development lifecycle, from specification drafting through system bring-up.
• Strong understanding of SystemVerilog and UVM verification methodologies.
• Strong background in AI/LLM accelerator or NPU design.
• Strong problem-solving skills, attention to detail, collaborative mindset, and written and verbal communication skills.
• B.S. or M.S. in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• Must be authorized to work in the U.S. without sponsorship.

Nice To Haves

• Experience with Altera (Intel) or AMD Xilinx FPGA architectures, EDA tools, and IP portfolios.
• Deep understanding of Ethernet protocols and the TCP/IP networking stack.
• Experience in microprocessor architecture, programmable logic design, or custom domain-specific accelerators.

Responsibilities

• Collaborate with the architecture team to define and refine the micro-architecture of next-generation FortiASICs.
• Partner with Design Verification teams to review test plans, perform coverage analysis, and execute full-chip simulations.
• Implement designs using SystemVerilog or Verilog HDL; conduct Lint and CDC reviews, logic synthesis, timing analysis, and IP integration.
• Work with physical design teams to verify constraints, optimize placement and routing, close timing, and achieve optimal Power, Performance, and Area.
• Emulate and prototype designs using FPGAs, and execute debugging and validation cycles.
• Participate in system- and board-level bring-up, post-silicon debugging, and ongoing technical support.
• Manage time effectively and collaborate with a diverse, cross-functional engineering team.

Benefits

• Medical, dental, vision, life, and disability insurance.
• 401(k).
• 11 paid holidays, vacation time, and sick time.
• Comprehensive leave program.
• Eligibility to participate in the Fortinet equity program.
• Bonus eligibility, reviewed at hire and annually at the Company's discretion.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal