Principal ASIC Design

Fortinet•Sunnyvale, CA

6h•$192,000 - $235,000

About The Position

Fortinet is seeking a passionate ASIC Designer to join its R&D team and help architect and design next-generation FortiASIC technology for network security systems. The role covers high-performance ASIC development from initial specification through RTL implementation, with a leading role in developing AI-powered network processing ASIC architecture, integrating IP, and delivering chip-level RTL design and verification. The position requires a strong technical foundation across the ASIC design lifecycle, including RTL design, chip-level verification, coverage analysis, and Static Timing Analysis (STA), as well as knowledge of computer networking, machine learning, LLM acceleration, and ASIC design methodologies. The role involves collaboration with architecture, design verification, physical design, and other engineering teams, along with FPGA prototyping, system and board-level bring-up, post-silicon debugging, and ongoing technical support. The successful candidate will be self-motivated, effective in a fast-paced environment with challenging schedules, and able to collaborate across functions. This is a full-time position with a US base salary range of $192,000–$235,000. Fortinet benefits include medical, dental, vision, life and disability insurance, a 401(k), 11 paid holidays, vacation and sick time, and a comprehensive leave program. Roles are eligible to participate in the Fortinet equity program; bonus eligibility is reviewed at hire and annually at the Company’s discretion. Applicants must be authorized to work in the U.S. without sponsorship.

Requirements

8+ years of experience in high-performance networking or processor design.
Proven track record of taking complex ASIC/FPGA designs from initial concept to mass production.
Hands-on expertise in Verilog/SystemVerilog HDL coding, synthesis, and design verification.
In-depth experience across the high-performance ASIC development lifecycle, from specification drafting through system bring-up.
Strong understanding of SystemVerilog and UVM verification methodologies.
Strong background in AI/LLM accelerator or NPU (Neural Processing Unit) design.
Strong problem-solving skills, attention to detail, a collaborative mindset, and strong written and verbal communication skills.
Must be authorized to work in the U.S. without sponsorship.
B.S. or M.S. in Electrical Engineering (EE), Computer Engineering (CE), Computer Science (CS), or a related technical field.

Nice To Haves

Experience with Altera (Intel) or AMD Xilinx FPGA architectures, EDA tools, and IP portfolios.
Deep understanding of Ethernet protocols and the TCP/IP networking stack.
Experience in microprocessor architecture, programmable logic design, or custom domain-specific accelerators.

Responsibilities

Collaborate with the architecture team to define and refine the micro-architecture of next-generation FortiASICs.
Partner with Design Verification teams to review test plans, perform coverage analysis, and execute full-chip simulations.
Implement designs using SystemVerilog/Verilog HDL; conduct Lint/CDC reviews, perform logic synthesis and timing analysis, and manage IP integration.
Work with physical design teams to verify constraints, optimize placement and routing, close timing, and achieve optimal Power, Performance, and Area (PPA).
Emulate and prototype designs using FPGAs, executing complete debug and validation cycles.
Participate in system- and board-level bring-up, post-silicon debugging, and ongoing technical support.
Manage time effectively and collaborate with a diverse, cross-functional engineering team.

Benefits

Medical insurance
Dental insurance
Vision insurance
Life insurance
Disability insurance
401(k)
11 paid holidays
Vacation time
Sick time
Comprehensive leave program
Equity program eligibility
Bonus eligibility, subject to review at hire and annually at the Company's discretion