ASIC Physical Design Principal Engineer

Cisco•San Jose, CA

1d•$250,600 - $416,900

About The Position

The ASIC Physical Design Principal Engineer will lead full-chip floorplanning and hierarchical RTL-to-GDSII implementation, optimizing performance, power, and die size. The role works across architecture, system, package, RTL, DFT, implementation, EDA vendors, foundry, and standard-cell IP teams to deliver design methodology and signoff. It also includes improving tool flows, applying low-power design methods using UPF, and using AI tools to improve productivity.

Requirements

Bachelor’s degree in Engineering and 15+ years of ASIC-related experience, Master’s degree in Engineering and 12+ years of ASIC-related experience, or PhD in Engineering and 7+ years of ASIC-related experience.
Experience with RTL-to-GDSII flows and design tapeouts in 7nm, 5nm, 3nm, or smaller process technologies.
Experience with EDA tools such as Innovus, Tempus/PrimeTime, RedHawk/Voltus, or Calibre/Pegasus.

Nice To Haves

Experience with full-chip activities, including floorplanning, power-grid planning, partitioning, and pin assignment.
Experience with hierarchical design, timing closure, physical-design convergence, and power-integrity analysis.
Experience with static timing analysis concepts, defining timing constraints and exceptions, and corner and voltage definitions.
Experience with custom chip-level clock structures such as H-Tree or mesh.
Experience with Python and using AI tools with accurate prompts.

Responsibilities

Develop full-chip floorplans based on design architecture, foundry integration guidelines, and IP placement constraints.
Collaborate with system and package design teams to understand requirements and incorporate them into the full-chip floorplan.
Perform hierarchical implementation, including partitioning, pin assignment, clock planning, and bump planning.
Use full-chip clock mesh and Flex-HTree methods.
Implement RTL-to-GDSII flows, including floorplanning, power-grid planning, place and route, static timing analysis, power integrity, physical verification, and equivalence checks, with a focus on performance, power, and die-size optimization.
Analyze existing tool flows and methodologies, identify efficiency gaps, and implement incremental or transformative enhancements.
Work with RTL, DFT, implementation, EDA vendor, and tool/flow teams to enable effective design methodology.
Apply low-power design methodologies using UPF.
Work with foundry and standard-cell IP vendors to define signoff methodologies and validate or adjust them based on feedback from post-silicon validation teams.
Use AI tools to improve productivity.

Benefits

Medical, dental, and vision insurance.
401(k) plan with a Cisco matching contribution.
Paid parental leave.
Short- and long-term disability coverage.
Basic life insurance.
Cisco restricted stock unit grants may be available, subject to eligibility and vesting conditions.
Paid holidays and a floating holiday for non-exempt employees.
Birthday day off, year-end holiday shutdown, and personal wellness days.
Paid vacation or flexible vacation time off, depending on employee classification and eligibility.
Paid sick time.
Additional paid time away may be requested for critical or emergency family issues.
Optional paid volunteer days.
Annual bonuses may be available for non-sales roles, subject to Cisco policies.