Senior ASIC Physical Design Engineer

Niobium

About The Position

Niobium Microsystems is seeking a highly experienced ASIC Physical Design Engineer to drive implementation of complex SoC designs from RTL handoff through tapeout. The role partners with Architecture, RTL Design, Verification, DFT, and Power teams to deliver high-performance, power-efficient silicon across advanced technology nodes. The position provides technical and organizational leadership for physical design, including ownership of schedules, methodology, quality, and tapeout execution. Niobium is headquartered in Columbus, Ohio, with additional locations in Fayetteville, Arkansas; Portland, Oregon; and Dayton, Ohio, and is not limited by geography for the right candidate.

Requirements

At least 8 years of relevant ASIC Physical Design experience.
A strong track record of multiple successful tapeouts at advanced technology nodes.
Deep expertise in floorplanning, place and route, CTS, STA/timing closure, physical verification and sign-off, and low-power design and UPF.
Strong hands-on proficiency with Cadence and/or Synopsys physical design toolchains.
Solid understanding of RTL-to-GDS flows, design architecture trade-offs, and SoC integration complexities.
Strong communication skills and ability to articulate technical decisions across cross-functional teams.
Highly motivated and proactive, with the ability to operate effectively in a distributed team environment.
Comfortable owning schedules, deliverables, and quality in a fast-moving development cycle.
Exceptional analytical, debugging, and problem-solving skills with meticulous attention to detail.
BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

Nice To Haves

Experience with advanced technology nodes from 16nm to 3nm is preferred.
An advanced degree is preferred for leadership roles.

Responsibilities

Own and lead physical design activities from RTL handoff, floorplanning, and place and route through final GDSII delivery.
Define execution strategy, schedules, design methodology, and quality checkpoints for the physical design flow.
Architect and execute floorplanning strategies for large hierarchical SoCs, including IP integration and macro placement, physical partitioning and hierarchy definition, power grid architecture, clock distribution topology, die size, aspect ratio, and physical constraints.
Collaborate with Architecture and RTL teams to ensure physical feasibility, timing closure readiness, and area and power targets.
Lead block-level and top-level place and route using industry-standard EDA tools.
Drive timing convergence across corners, modes, voltage domains, and operating conditions.
Own PPA optimization, congestion mitigation, and physical integrity.
Implement clock tree synthesis and optimize skew, latency, and clock power.
Lead IR/EM sign-off strategy, thermal analysis, and full-chip physical verification, including DRC, LVS, and ERC.
Integrate and validate low-power methodologies, including UPF/CPF flows.
Partner with DFT and physical design teams to ensure scan insertion, BIST structures, and test modes are physically robust and timing clean.
Work with Packaging and SI teams on bump planning, floorplan constraints, and package-aware timing.
Set physical design quality standards, conduct design reviews, and ensure execution through tapeout.
Provide technical leadership to junior and mid-level physical designers; mentor and guide engineers in methodology, debugging, and best practices.
Champion continuous improvement across flows, scripts, and design methodology.
Translate product requirements into physical design goals, budgets, constraints, and deliverable plans.