Senior ASIC Physical Design Engineer

Hewlett Packard Enterprise•Fort Collins, CO

4d•$147,000 - $279,000•Hybrid

About The Position

HPE is seeking an experienced ASIC Physical Design Engineer to support the development of complex, high-performance integrated circuits. In this role, you will contribute to design quality, synthesis, formal verification, partitioning, floorplanning, timing analysis, timing closure, and signoff activities. You will collaborate closely with ASIC design, physical implementation, DFT, signal integrity, architecture, and other cross-functional teams to develop physically aware designs and scalable implementation methodologies. This role offers the opportunity to work with advanced process technologies and contribute to complex ASIC products and platforms.

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, Microelectronics, or a related technical field.
Typically 6–10 years of experience in ASIC, VLSI, or semiconductor design implementation, with relevant experience in physical design and timing closure.
Strong understanding of digital logic, circuit design, computer architecture, VLSI principles, and ASIC physical design.
Experience with one or more of the following: Static timing analysis and timing signoff, Timing constraints and validation, Synthesis and netlist quality analysis, Formal verification, Floorplanning and chip partitioning, ECO implementation
Experience with industry-standard EDA tools, such as Synopsys Fusion Compiler, Design Compiler, PrimeTime, or Formality, and/or Cadence RTL Compiler, Genus, or LEC.
Proficiency in scripting and flow automation using Perl, Python, Tcl, or similar languages.
Strong analytical, problem-solving, and debugging skills.
Effective written and verbal communication skills in English.
Ability to work independently and collaboratively across multiple engineering disciplines.

Nice To Haves

Experience with hierarchical timing analysis and full-chip timing closure.
Experience with clock, I/O, test, and other specialized timing-closure challenges.
Experience developing ASIC implementation flows, automation, and design methodologies.
Experience working with advanced process technologies and complex, high-performance ASIC designs.
Demonstrated ability to provide technical leadership, mentor engineers, and influence cross-functional design decisions.
Graduate coursework or a Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or Microelectronics.
Publications, patents, or other demonstrated contributions in ASIC, VLSI, physical design, or electronic design automation.

Responsibilities

Perform static timing analysis for hierarchical designs at both partition and full-chip levels.
Create, validate, and maintain timing constraints and timing budgets for design and process requirements.
Drive timing closure for partition-level and full-chip designs, including setup, hold, clock, I/O, and test timing.
Analyze timing reports, identify critical paths, and implement fixes to achieve performance, power, and area objectives.
Perform synthesis, netlist quality checks, and formal verification.
Support chip partitioning, floorplanning, and physical design implementation.
Create and manage functional engineering change orders (ECOs).
Develop flow automation and methodology improvements for synthesis, timing analysis, formal verification, physical design, and signoff.
Partner with cross-functional engineering teams to promote physical-design-aware architecture and implementation.
Review design and project activities for compliance with ASIC technology, methodology, and development standards.
Provide technical guidance and mentoring to less-experienced engineers and contribute to continuous improvement across the design organization.