Principal ASIC Design Engineer - Chip Lead

CesiumAstro•Aliso Viejo, CA

About The Position

Jariet Technologies, Inc., a subsidiary of CesiumAstro, is developing CMOS-based digital communications technologies for micro- and millimeter-wave applications. The company is seeking a Principal ASIC Design Engineer to serve as Chip Lead for next-generation high-speed mixed-signal and DSP projects. The role calls for cradle-to-grave experience across large, high-speed communications chip design, from concept and architecture through silicon bring-up, release, and volume production. The successful candidate will lead chip design activities spanning system simulation, RTL implementation and verification, synthesis, and coordination with backend teams. The position also involves high-speed analog block integration, analysis of specifications to identify architectural and microarchitectural improvements, program and people management, project tracking, and communication with customers and marketing or sales teams. U.S. government space technology export regulations require applicants to be a U.S. citizen, lawful permanent resident, conditional resident, asylee, refugee, or otherwise eligible to obtain the required authorizations.

Requirements

Master’s degree in Engineering.
At least 10 years of experience.
Experience with the IC/ASIC development flow from concept through production release of silicon.
Experience defining and using front-end design flows from system simulation through RTL implementation, verification, synthesis, and backend-team interfacing.
Experience integrating high-speed analog blocks into digital logic.
Ability to analyze specifications at the architecture and microarchitecture levels and identify design improvements.
Strong program management, people management, and project tracking skills.
Experience with customer communications and marketing/sales interactions.
Experience with ASIC verification using a random constraint coverage-driven methodology such as UVM, VMM, OVM, or SPECMAN.
Fluency with Verilog and SystemVerilog.
Experience with synthesis, formal verification, and STA flow setup.
Must meet the stated U.S. space technology export-control eligibility requirements or be eligible to obtain the required authorizations.

Nice To Haves

Experience with low-power design flows.
Experience implementing DSP blocks.
Knowledge of digital communications systems, DSP, ASIC microarchitecture, analog IP integration, embedded processors, high-level verification, RTL design with multiple asynchronous clock domains, timing analysis, DFT, backend flow, chip bring-up, debug, lab testing, and product transition through volume production.

Responsibilities

Lead chip design for next-generation high-speed mixed-signal and DSP projects.
Work across the IC/ASIC development lifecycle, from concept through production release of silicon.
Define and use front-end design flows spanning system simulation, RTL implementation, verification, synthesis, and coordination with a backend team.
Integrate high-speed analog blocks into digital logic.
Analyze specifications at the architecture and microarchitecture levels to identify design improvements.
Manage programs, people, and project tracking.
Interact with customers and participate in marketing and sales communications.
Support chip bring-up, debug, lab testing, and transition from first sample through release to volume production.