ASIC Physical Design Principal Engineer
About The Position
The Common Hardware Group (CHG) develops hardware platforms for Cisco’s switching, routing, and wireless products, including innovations in silicon, optics, and hardware platforms such as Silicon One. The team handles full product development, from design through qualification and production. The ASIC Physical Design Principal Engineer will lead full-chip floorplanning and hierarchical RTL-to-GDSII implementation, considering design architecture, foundry integration guidelines, IP placement constraints, and system and package requirements. The role covers implementation activities from floorplanning and power-grid planning through place and route, timing analysis, power integrity, physical verification, and equivalence checks, with a focus on optimizing performance, power, and die size. It also involves improving tool flows and methodologies, collaborating with design and vendor teams, defining and validating signoff methodologies, and applying AI tools to improve productivity.
Requirements
- Bachelor’s degree in Engineering and 15 or more years of ASIC-related experience; or a Master’s degree in Engineering and 12 or more years of ASIC-related experience; or a PhD in Engineering and 7 or more years of ASIC-related experience.
- Experience with RTL-to-GDSII flows and design tapeouts using 7nm, 5nm, 3nm, or smaller process technologies.
- Experience with EDA tools such as Innovus, Tempus or PrimeTime, RedHawk or Voltus, or Calibre or Pegasus.
Nice To Haves
- Experience with full-chip activities, including floorplanning, power-grid planning, partitioning, and pin assignment.
- Experience with hierarchical design, timing closure, physical-design convergence, and power-integrity analysis.
- Experience with static timing analysis concepts, defining timing constraints and exceptions, and corner and voltage definitions.
- Experience with custom chip-level clock structures such as H-Tree or mesh.
- Experience with Python and using AI tools through accurate prompting.
Responsibilities
- Develop full-chip floorplans based on design architecture, foundry integration guidelines, and IP placement constraints.
- Collaborate with system and package design teams to incorporate their requirements into the full-chip floorplan.
- Perform hierarchical implementation, including partitioning, pin assignment, clock planning, and bump planning.
- Apply full-chip clock mesh and Flex-HTree methods.
- Implement RTL-to-GDSII flows, including floorplanning, power-grid planning, place and route, static timing analysis, power integrity, physical verification, and equivalence checks.
- Optimize performance, power, and die size.
- Analyze existing tools and methodologies, identify efficiency gaps, and implement incremental or transformative improvements.
- Work with RTL, DFT, implementation, EDA vendor, and tool/flow teams to enable design methodology improvements.
- Use low-power design methodologies with UPF.
- Work with foundry and standard-cell IP vendors to define signoff methodologies and validate or adjust them based on feedback from Post-Silicon Validation teams.
- Use AI tools to improve productivity.
Benefits
- Medical insurance
- Dental insurance
- Vision insurance
- 401(k) plan with Cisco matching contribution
- Paid parental leave
- Short- and long-term disability coverage
- Basic life insurance
- Paid holidays
- Floating holiday for non-exempt employees
- Paid birthday day off
- Paid year-end holiday shutdown
- Paid personal wellness days
- Paid vacation or flexible vacation time off, depending on employee classification
- Paid sick time
- Additional paid time away may be requested for critical or emergency family issues
- Optional paid volunteer days
- Annual bonuses for eligible non-sales roles
- Potential Cisco restricted stock unit grants
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What This Job Offers
Job Type
Full-time
Career Level
Principal
