ASIC Chip Lead and Design Engineer

Chelsea Search Group•Minneapolis, MN

About The Position

Design and deliver complex, custom ASICs from concept through silicon. This hands-on role works across the full ASIC/SoC development flow and collaborates with architecture, verification, physical design, applications, and business teams to translate technical requirements into high-performance silicon while optimizing power, performance, and area (PPA). The engineer will also evaluate customer requirements, develop technical approaches and effort estimates for new opportunities, and help improve internal design methodologies and processes. Additional experience in radiation-hardened design, analog/mixed-signal circuits, EDA methodologies, or standard-cell library development may be applied and expanded.

Requirements

BSEE, MSEE, or equivalent.
10 or more years of direct industry experience with ASIC and/or SoC design.
Proficiency in Synopsys Design Compiler and other EDA tools.
Strong understanding of digital design principles.
Familiarity with RISC architectures such as ARM or MIPS.
Strong background in RTL-based digital IC design using Verilog/SystemVerilog.
Proven track record of first-pass successes.
Proficiency with UNIX/Linux, including shell scripting, text utilities such as sed, awk, and grep, and using Modules.
Experience with C/C++ and PERL, Python, or TCL scripting.
Proficiency with Windows applications, including Word, Excel, PowerPoint, Visio, Project, and PDF conversion.
Excellent problem-solving skills and attention to detail.
Self-starter with the ability to assume leadership roles.
Ability to work well in a diverse team environment.
Willingness to mentor junior engineers.
Experience with industry-standard development tools and methodologies.

Nice To Haves

Experience in radiation-hardened design.
Experience with analog/mixed-signal circuits.
Experience with EDA methodologies.
Experience with standard-cell library development.

Responsibilities

Lead ASIC architectural design based on high-level requirements and block diagrams.
Collaborate with system architects to define chip functionality, interfaces, and performance targets.
Develop detailed specifications for chip components.
Create RTL designs using Synopsys Design Compiler and optimize RTL for area, power, and performance.
Implement and verify complex digital blocks.
Develop timing constraints for the entire chip.
Work with physical design teams to support successful place-and-route, including floorplanning, placement, routing, and design closure.
Constrain and verify RISC processors within the chip, and optimize processor performance and power efficiency.
Work with verification engineers to ensure functional correctness and assist with testbench creation and chip functionality verification.
Evaluate customer requirements and develop technical approaches and effort estimates for new opportunities.
Contribute to improvements in internal design methodologies and processes.
Use modern revision-control tools and collaborative best practices in a multi-site design community.
Mentor junior engineers.