ASIC Design Engineer

Hewlett Packard Enterprise•Sunnyvale, CA
•$124,000 - $251,000•Hybrid

About The Position

HPE Networking Silicon builds advanced networking chips for routers and switches. As part of a fast-paced silicon group, the ASIC Design Engineer works on high-speed ASICs from specifications through final netlist, designing complex modules and subsystems that meet power, area, and frequency targets. The role collaborates with Physical Design and Verification teams and may include mentoring new college graduates and interns. The position is hybrid, with an average of two days per week in an HPE office.

Requirements

  • Bachelor’s degree in Electrical Engineering.
  • At least 4 years of relevant experience.
  • Strong analytical and problem-solving skills.

Nice To Haves

  • Master’s degree in Electrical Engineering is strongly desired.
  • Knowledge of computer architecture or networking protocols through graduate-level coursework or prior work.
  • Strong Verilog/SystemVerilog coding skills demonstrated through coursework, projects, or work experience.
  • Knowledge of synthesis, lint, and other state-of-the-art EDA tools.
  • Excellent written and verbal communication skills.
  • Knowledge of Perl or Python.
  • Experience with AI agentic tools.

Responsibilities

  • Translate a module’s functional specification into a detailed micro-architecture specification that meets power and area requirements.
  • Implement designs using Verilog or SystemVerilog.
  • Write functional coverage and SVA to help verification identify corner-case bugs.
  • Work with the Physical Design team on floorplanning and timing closure; identify and fix RTL timing issues to meet frequency targets.
  • Work with the Verification team to ensure blocks are fully validated.
  • Provide mentoring and guidance to new college-graduate engineers and interns.

Benefits

  • Comprehensive benefits intended to support physical, financial, and emotional wellbeing.
  • Career development programs to support professional growth and career goals.
  • Variable incentives may be offered.
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