ASIC Package Design Engineer

Broadcom•Fort Collins, CO

1d•$143,800 - $230,000•Onsite

About The Position

Broadcom is seeking an experienced IC package-design engineer to design complex flip-chip BGA packages for leading ASICs with high-speed SerDes and very high-power-delivery needs. The role is part of a worldwide R&D team developing high-performance ASIC packages for artificial intelligence, networking, high-performance computing, and 5G base stations. Designs include SerDes at 448G and higher, 5G RF/Microwave ADC/DAC, HBM, and DDR5. The engineer will collaborate with the team to create package structures that enable new designs and contribute to design-team efficiency improvements. Physical design (layout) is a foundational responsibility. The role has overall design responsibility for ASIC package designs, including signal integrity, power integrity, manufacturability, reliability, and thermal considerations, in partnership with package engineering experts. It also includes project scheduling and tracking, project management, and customer interface. This position requires working on-site at the Broadcom office five days a week and is not remote. The annual base salary range is USD 143,800 to USD 230,000. Eligible compensation also includes a discretionary annual bonus and the opportunity for new-hire and annual equity awards, subject to applicable plan documents and award agreements.

Requirements

BSEE or a similar field and 12 or more years of experience in flip-chip BGA package design, including high-speed SerDes; alternatively, an MSEE or similar field and 10 or more years of work experience.
Knowledge of package-level signal integrity and power integrity and the ability to apply that knowledge to package designs.
Ability to cooperate with a worldwide team across multiple time zones, including co-design with internal team members and external vendor designers.
Self-management and organization skills.

Nice To Haves

Cadence APD (Allegro Package Designer) experience; an equivalent tool is acceptable.
One or more years of experience with Cadence SKILL for Allegro, or similar design-automation coding experience and interest.

Responsibilities

Own overall design responsibility for ASIC package designs, including signal integrity, power integrity, manufacturability, reliability, and thermal considerations, in partnership with the package engineering team.
Design critical package structures for SerDes, ADC/DAC, DDR, HBM, and related technologies.
Schedule, prioritize, and track work across two or more projects simultaneously.
Perform general flip-chip BGA package design and engineering.
Manage projects and serve as the customer interface for assigned design projects.
Contribute to design-team efficiency improvements through process development and improvement, automation, and documentation.
Perform physical design (layout), a foundational responsibility of the role.

Benefits

Discretionary annual bonus
Opportunity for a competitive new-hire equity grant and annual equity awards
Medical insurance
Dental insurance
Vision insurance
401(k) participation with company matching
Employee Stock Purchase Program (ESPP)
Employee Assistance Program (EAP)
Company-paid holidays
Paid sick leave
Vacation time
Paid Family Leave and other leaves of absence in accordance with applicable laws