The ASIC DFT STA Engineer will work in Cisco’s Silicon One development organization on next-generation networking chips. The role focuses on static timing analysis, timing constraints, and driving design-for-test (DFT) and quality processes through implementation and post-silicon validation, with additional exposure to physical design signoff. The engineer will collaborate with cross-functional teams and communicate complex timing data clearly. Candidates should bring strong analytical skills and a detailed understanding of timing constraints, including clock groups, exceptions, and clock exclusivity.
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Job Type
Full-time
Career Level
Senior