The ASIC Technical Leader – DFT will work in Cisco’s Silicon One development organization within the Common Hardware Group. The role partners with front-end RTL and backend physical design teams to understand chip architecture and establish DFT requirements early in the design cycle. The position contributes to developing next-generation networking chips and leads DFT and quality processes throughout implementation and post-silicon validation, with additional exposure to physical design signoff activities.
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Job Type
Full-time
Career Level
Senior