The ASIC DFT STA Engineer will work in Cisco’s Silicon One development organization, helping develop next-generation networking chips. The role focuses on static timing analysis and timing constraints, including clock groups, timing exceptions, and clock exclusivity. The engineer will collaborate with cross-functional teams and communicate timing analysis clearly. They will help drive design-for-test (DFT) and quality processes throughout implementation and post-silicon validation, with additional exposure to physical design signoff activities.
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Job Type
Full-time
Career Level
Senior