Asic Design Engineer Jobs

About The Position

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• At least 8 years of design verification experience.
• Experience verifying ASIC digital logic at RTL using SystemVerilog and Universal Verification Methodology (UVM).

Nice To Haves

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
• 10 years of experience with industry-standard tools, languages, and methodologies relevant to developing silicon-based integrated circuits and chips.
• Experience with the full verification life cycle.
• Experience with three or more SoC projects or cycles and verification of interconnect IPs.

Responsibilities

• Plan verification for complex digital design blocks by interpreting specifications and working with design engineers to identify important verification scenarios.
• Create and enhance constrained-random verification environments using SystemVerilog and UVM.
• Identify and write coverage measures for stimulus and corner cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Close coverage measures to identify verification gaps and demonstrate progress toward tape-out.
• Participate in the architecture, documentation, and verification of next-generation data center accelerators.

Benefits

• 15% bonus target
• Equity
• Benefits (specific benefits are not listed in the posting)