Staff Engineer, ASIC Analog Design – AI/CAD

Micron • Minneapolis, MN

4d

About The Position

Micron Technology is seeking an ASIC Analog Design Engineer for its ASIC design team, focused on supporting the AI and Virtuoso design environment. The role contributes to ASICs used in Micron's tester and controller IP, working with a high-speed PHY design team on deep sub-micron technology nodes. The engineer may flex among analog environment maintenance, flow development, and traditional schematic and layout design according to group needs.

The position supports and improves analog front-end and back-end tools and flows, maintains knowledge sources that improve AI-agent effectiveness, and explores ways to increase design efficiency and quality. Design work includes proposing circuit architectures, refining electrical specifications, drawing schematics, verifying designs through simulation, and communicating design choices, tradeoffs, and alternatives to the design team and customers.

Requirements

• B.S., M.S., or Ph.D. in Electrical Engineering.
• More than 6 years of ASIC analog design experience.
• Understanding of basic generative AI principles and interest in using AI-enabled automation to maximize design efficiency.
• Strong understanding of industry-standard tools and flows, including Cadence ADE, Spectre, front- and back-end verification, Pegasus, Quantus, field solvers (EMX, Helic), EM/IR, LVS/ERC/DRC, PERC, Pathfinder, Fill, and advanced PDKs.
• Strong fundamentals in analog and mixed-signal design, advanced CMOS, and FinFET technologies.
• Strong written and verbal communication skills.
• Deep understanding of analog and mixed-signal circuits.
• Understanding of mismatch analysis, Monte Carlo methods and simulations, transistor-level circuit noise analysis, device physics, and deep sub-micron issues.
• Curiosity and willingness to contribute, learn, and grow.

Nice To Haves

• Extensive knowledge of generative AI principles.
• Extensive background in Virtuoso analog design tools, flows, PCells, and TSMC PDKs.
• Experience with software basics.
• Working knowledge of Git repositories.
• Experience developing scripts in Python and Cadence's SKILL language.
• Knowledge of system-level modeling using VerilogA or Python.

Responsibilities

• Work as part of a high-speed PHY design team on deep sub-micron technology nodes.
• Flex among environment maintenance, flow development, and schematic/layout design as group needs require.
• Enhance and debug the analog environment for front-end and back-end tools and flows.
• Maintain knowledge graphs, graphRAG, or other information sources to improve AI-agent effectiveness.
• Explore ways to improve design efficiency and quality.
• Propose circuit architectures, refine electrical specifications, draw schematics, and verify designs through simulation.
• Present designs and complex engineering ideas to the design team and customers, including explaining design choices and tradeoffs.
• Explore the design space and provide feedback on design tradeoffs, alternative circuit architectures, and specification and requirement tradeoffs.

Benefits

• Choice of medical, dental, and vision plans.
• Income-protection benefit programs for illness or injury.
• Paid family leave.
• Paid time off.
• Paid holidays.
• Additional compensation may include bonuses and equity.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior