ASIC Analog Design Engineer

Micron•Minneapolis, MN

3d•$106,000 - $179,000

About The Position

As an ASIC Analog Design Engineer on Micron's ASIC analog design team, you will help shape ASICs used in Micron's tester and controller IP. The role involves designing and developing high-speed PHYs in deep sub-micron technologies. Candidates who meet the minimum qualifications may be considered across multiple experience levels. You will work with a high-speed PHY design team to develop circuit architectures and specifications, create and verify schematics, guide analog layout, and investigate performance issues. You will also collaborate with package, board, and validation teams; support silicon bring-up and characterization; and communicate design choices and tradeoffs to engineering colleagues and customers. This is a full-time position. The estimated US base salary range is $106,000 to $179,000 per year. Additional compensation may include benefits, bonuses, and equity. Micron offers medical, dental, and vision plans, income-protection programs, paid family leave, paid time off, and paid holidays.

Requirements

B.S., M.S., or Ph.D. in Electrical Engineering.
ASIC analog design experience.
Strong fundamental knowledge of analog and mixed-signal design, advanced CMOS, and FinFET technologies.
Strong written and verbal communication skills.
Deep understanding of analog and mixed-signal circuits.
Understanding of architectural tradeoffs in high-speed SerDes and PHYs.
Understanding of mismatch analysis, Monte Carlo methods and simulations, transistor-level circuit noise analysis, device physics, and deep sub-micron issues.
Experience with industry-standard tools and flows, including Cadence ADE, Spectre, AMS verification, EM/IR flows, MATLAB, and Pegasus.
Understanding of the fundamentals of signal integrity, power delivery, and ESD.
Interest in utilizing AI-enabled automation to maximize design efficiency.
Curiosity and willingness to contribute, learn, and grow.

Nice To Haves

Experience designing circuits to standards for high-speed memory interfaces (DDR3/4/5, LPDDR3/4x/5, GDDR5/6) or SerDes interfaces (PCIe, M-PHY, HDMI, USB, SATA).
Prior experience taking full ownership of at least one sub-block, such as a PLL, DLL, CDR, high-speed receiver with equalization, transmitter front end, or high-speed data path.
Knowledge of system-level modeling using VerilogA or Python.

Responsibilities

Propose circuit architectures and refine electrical specifications.
Draw schematics, verify designs through simulation, and present designs to the design team.
Supervise complex and/or sensitive analog layout and define block floorplans.
Investigate parasitics to debug and resolve layout-related performance issues.
Present complex engineering ideas to the design team and customers, explaining design choices and tradeoffs.
Explore the design space and provide feedback on design tradeoffs, alternative circuit architectures, and specification and requirement tradeoffs.
Align requirements and provide feedback to package and board teams.
Plan and participate in silicon bring-up and characterization, and correlate results with simulations.
Work with the validation team to perform tests, analyze data, and design experiments to resolve challenging silicon debug issues.