Principal Analog/Mixed-Signal ASIC Design Engineer

Taara•Sunnyvale, CA

4d•$258,000 - $294,000

About The Position

Taara, born at X, Google's Moonshot Factory, is working to connect people who lack abundant and affordable internet through high-throughput, long-range free-space optical communication. Its links use eye-safe lasers between terminals to transmit high-speed data wirelessly. Taara is seeking a Principal Analog/Mixed-Signal ASIC Design Engineer to develop the next generation of co-integrated electronic and photonic modules. As part of an R&D team developing wireless optical communication systems based on integrated optical phased arrays, you will own ASIC design blocks and contribute to ASIC tape-out, delivery, and validation. The work involves hands-on analog/mixed-signal ASIC design, verification, and layout, in collaboration with a small team of ASIC design, layout, and test engineers. The role calls for extensive ASIC design experience, including multiple tape-outs at leading commercial foundries, and deep expertise in high-precision analog/mixed-signal circuits. The position is intended for someone motivated to work through ambiguity in a small, dynamic team and solve challenging problems with high-impact technological outcomes. The role is preferred hybrid or onsite in Sunnyvale, California, though remote work can be considered. Relocation assistance can be provided. The US salary range is $258,000–$294,000, inclusive of bonus at target, plus equity and benefits. Pay within the range depends on work location and factors such as job-related skills, experience, and relevant education or training.

Requirements

Ph.D. in Electrical Engineering or a related field.
At least 10 years of relevant industry experience with demonstrated achievements in analog/mixed-signal circuit design and implementation in modern CMOS technologies.
Deep design expertise in high-precision circuits, including analog-to-digital and digital-to-analog converters, bandgap references, voltage regulators, amplifiers, and supporting circuitry.
Tape-out experience in high-voltage Bipolar-CMOS-DMOS (BCD) technology, including successful silicon bring-up and characterization.
Extensive experience integrating and co-simulating analog and digital circuits for mixed-signal design and verification.
Hands-on experience contributing to multiple ASIC tape-outs at commercial foundries, including chip top-level ownership.
Hands-on experience with Design Rule Checks (DRC), Layout Versus Schematic (LVS), Power Integrity (PI), and Signal Integrity (SI) verification.

Nice To Haves

Expertise in planning and executing verification of large Systems-on-Chip (SoCs) with complex digital logic and numerous custom-designed blocks.
Fluency in hardware description languages, such as Register-Transfer Level (RTL) code, and RTL-to-GDS design flows using industry-standard EDA tools.
Experience with versioning tools such as SOS and Git.
Proficiency with commercial layout verification software such as Calibre or equivalent.
Excellent communication and presentation skills, including the ability to work effectively with senior external partners.
A track record of advancing a product from prototype through final production.

Responsibilities

Own and deliver custom ASIC blocks for co-integration with large-scale photonic integrated circuits.
Contribute to chip architecture, system-level optimization, and product strategy.
Contribute to ASIC tape-out, delivery, and validation.
Perform hands-on analog/mixed-signal ASIC design, verification, and layout.
Work with ASIC design, layout, and test engineers.