VLSI ASIC Logic Design Engineer

Hewlett Packard Enterprise•Frisco, CO

2d•Hybrid

About The Position

Hewlett Packard Enterprise is hiring a VLSI ASIC Logic Design Engineer to design, analyze, develop, modify, and evaluate VLSI components and hardware systems. The work includes determining architecture and logic design, verifying designs through software-based component and system simulation, and developing physical implementations of complex integrated circuits. The engineer analyzes designs, conducts experimental tests, and evaluates results to support prototype and production VLSI solutions. As an independent project-team member, the engineer works with other VLSI engineers and internal and outsourced development partners to develop reliable, cost-effective, high-quality VLSI prototypes and products. The role includes SystemVerilog RTL design, formal verification, coverage development and analysis, and creation of documentation that communicates design intent to verification and firmware teams. The engineer also explores system latency and bandwidth trade-offs, identifies bottlenecks, and proposes solutions. The position may involve acting as a project lead and mentoring less experienced staff. The position is hybrid, with an average requirement of two days per week working from an HPE office.

Requirements

Bachelor's or master's degree in Electrical Engineering, Computer Engineering, or equivalent.
1–6 years of experience in VLSI design, verification, or implementation.
Strong knowledge of electrical engineering fundamentals, VLSI principles, digital logic, and computer architecture.
Strong analytical and problem-solving skills.
Strong experience designing VLSI components, integrated circuitry, architectures, and algorithms.
Strong knowledge of programming and scripting, hardware description languages, electronic design automation (EDA), and/or FPGA tools.
Coursework in VLSI design or VLSI concepts.
Strong written and verbal communication skills; mastery of English and the local language.
Subject-matter knowledge in major areas of responsibility, with growing breadth of understanding and depth of specific expertise.

Nice To Haves

Understanding of the OSI model for layered networking stacks.
Experience with Ethernet protocols, CPU or GPU systems, and high-speed peripherals.
Experience with formal verification and design verification using UVM.

Responsibilities

Design VLSI and RTL using SystemVerilog.
Create SystemVerilog Assertions (SVAs) and use formal verification to prove design correctness.
Write coverage to measure stimulus quality and analyze coverage to identify verification holes.
Create documentation that communicates design intent and guides verification and firmware teams in using design features.
Explore system latency and bandwidth trade-offs, identify bottlenecks, and propose solutions.
Collaborate and communicate with management and internal partners about design status, project progress, and issue resolution.
Work as an independent project-team member with VLSI engineers and internal and outsourced development partners to develop reliable, cost-effective, high-quality VLSI prototypes and products.
Provide guidance and mentoring to less experienced staff.