VLSI ASIC Logic Design Engineer

Hewlett Packard Enterprise•Fort Collins, CO

3d•$109,000 - $251,000•Hybrid

About The Position

Hewlett Packard Enterprise is hiring a VLSI ASIC Logic Design Engineer to design, analyze, develop, modify, and evaluate VLSI components and hardware systems. The role involves determining architecture and logic design, verifying designs through software-based component and system simulation, and developing physical implementations of complex integrated circuits. The engineer analyzes designs, conducts experimental tests, and evaluates results to enable prototype and production VLSI solutions. The role may also involve directing support personnel in detailed design, testing, and prototype fabrication. The engineer works independently as part of project teams with other VLSI engineers and internal and outsourced development partners to develop reliable, cost-effective, high-quality VLSI prototypes and products. The position applies subject-matter expertise to technical problems, may lead projects, exercises independent judgment, and may guide and mentor less experienced staff. It is hybrid, requiring an average of two days per week at an HPE office.

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent.
1–6 years of experience in VLSI design, verification, or implementation.
Strong knowledge of electrical engineering fundamentals, VLSI principles, digital logic, and computer architecture.
Strong analytical and problem-solving skills.
Strong experience designing VLSI components, integrated circuitry, architectures, and algorithms.
Strong knowledge of programming and scripting, hardware description languages, electronic design automation (EDA), and/or FPGA tools.
Coursework in VLSI design or VLSI concepts.
Strong written and verbal communication skills, with mastery of English and the local language.
Subject-matter knowledge in major areas of responsibility, with growing breadth of understanding and depth of specific expertise.

Nice To Haves

Understanding of the OSI model for layered networking stacks.
Experience with Ethernet protocols, CPU or GPU systems, and high-speed peripherals.
Experience with formal verification and design verification using UVM.

Responsibilities

Design VLSI/RTL using SystemVerilog.
Create SystemVerilog Assertions (SVAs) and use formal verification to prove design correctness.
Write coverage to measure stimulus quality and analyze coverage to identify verification gaps.
Create documentation that communicates design intent and guides verification and firmware teams in using design features.
Explore system latency and bandwidth trade-offs, identify bottlenecks, and propose solutions.
Collaborate and communicate with management and internal partners about design status, project progress, and issue resolution.
Participate as an independent project team member with VLSI engineers and internal and outsourced development partners to develop reliable, cost-effective, high-quality VLSI prototypes and products.
Provide guidance and mentoring to less experienced staff members, setting an example of VLSI design and development innovation and excellence.