ASIC Chip Lead and Design Engineer (remote)

Chelsea Search Group•Hillsboro, OR
•Remote

About The Position

Lead and contribute hands-on to the design and delivery of complex custom ASICs from concept through silicon. Work across the full ASIC/SoC development flow and collaborate with architecture, verification, physical design, applications, and business teams to translate technical requirements into high-performance silicon while optimizing power, performance, and area (PPA). The role also involves evaluating customer requirements, developing technical approaches and effort estimates for new opportunities, and improving internal design methodologies and processes. Additional expertise in radiation-hardened design, analog/mixed-signal circuits, EDA methodologies, or standard-cell library development may be applied and expanded.

Requirements

  • BSEE, MSEE, or equivalent.
  • 10+ years of direct industry experience with ASIC and/or SoC design.
  • Proficiency in Synopsys Design Compiler and other EDA tools.
  • Strong understanding of digital design principles.
  • Familiarity with RISC architectures such as ARM or MIPS.
  • Strong background in RTL-based digital IC design using Verilog/SystemVerilog.
  • Proven track record of first-pass successes.
  • Excellent problem-solving skills and attention to detail.
  • Ability to take initiative and assume leadership roles.
  • Ability to work well in a diverse team environment.
  • Willingness to mentor junior engineers.
  • Experience with industry-standard development tools and methodologies.
  • Proficiency with UNIX/Linux, including shell scripting, text utilities such as sed, awk, and grep, and using Modules.
  • Experience with high-level programming and scripting, including C/C++, PERL, Python, and TCL.
  • Proficiency with Windows applications including Word, Excel, PowerPoint, Visio, Project, and PDF conversion.

Nice To Haves

  • Experience in radiation-hardened design.
  • Experience with analog/mixed-signal circuits.
  • Experience with EDA methodologies.
  • Experience with standard-cell library development.

Responsibilities

  • Lead ASIC architectural design based on high-level requirements and block diagrams.
  • Collaborate with system architects to define chip functionality, interfaces, and performance targets.
  • Develop detailed specifications for chip components.
  • Create and optimize RTL designs using Synopsys Design Compiler, focusing on area, power, and performance.
  • Implement and verify complex digital blocks.
  • Develop timing constraints for the entire chip and work with physical design teams to support successful place-and-route.
  • Constrain and verify RISC processors within the chip, and optimize processor performance and power efficiency.
  • Collaborate with physical design teams on floorplanning, placement, and routing, and address design closure issues.
  • Work with verification engineers to ensure functional correctness and assist with testbench creation and chip verification.
  • Evaluate customer requirements and develop technical approaches and effort estimates for new opportunities.
  • Influence improvements to internal design methodologies and processes.
  • Use modern revision-control tools and best practices in a collaborative, multi-site design community.
  • Mentor junior engineers.
© 2026 Teal Labs, Inc
Privacy PolicyTerms of Service