ASIC Design Engineer – Clocks IP

NVIDIA•Austin, TX

9d•$116,000 - $218,500•Hybrid

About The Position

The Clocks team is responsible for designing GPU and CPU clocking. It collaborates with front-end design teams to understand chip clocking requirements, works with floor-planning and back-end teams on the physical floorplan, explains the programming model to software teams, and works with silicon solution teams to triage silicon or programming bugs in the lab. As a Clocks team member, the engineer architects clock domains to satisfy functional, physical, and testing requirements. The role involves designing GPU or CPU clocks within architectural, design, and physical constraints; improving power, performance, and area (PPA) through trade-off evaluation and new RTL clocking topologies; collaborating with physical design and timing teams on high-speed clocking; delivering clock RTL information to GPU, CPU, SoC verification, timing, and DFT teams; and participating in the ASIC execution cycle from microarchitecture through implementation, fixes, sign-off, and silicon bring-up.

Requirements

Bachelor's degree in Electrical Engineering or equivalent experience; a master's degree is preferred.
At least 2 years of relevant work experience.
Deep understanding of logic optimization techniques and PPA trade-offs.
Excellent interpersonal skills and ability to collaborate with multiple teams.
Experience in RTL design using Verilog, verification, and logic synthesis.
Strong coding skills in Python or other industry-standard scripting languages.

Nice To Haves

Understanding of sub-micron silicon issues such as noise, crosstalk, and OCV effects.
Experience implementing on-chip clocking networks.
Experience with clock controllers and clock logic design.
Understanding of system-level artifacts such as power and noise.
Experience with scalable designs and architecture.
Hands-on silicon debug experience.

Responsibilities

Architect clock domains to satisfy functional, physical, and testing design requirements.
Engage with multiple teams to design GPU or CPU clocks that meet architectural, design, and physical constraints.
Improve PPA by evaluating trade-offs across DFX, physical implementation, power optimization, and timing closure, and by developing and implementing new clocking topologies in RTL.
Collaborate with physical design and timing teams to evaluate clocking concerns and develop solutions for high-speed clocking.
Deliver clock RTL information to GPU, CPU, and SoC verification teams, as well as timing and DFT teams.
Participate in the end-to-end ASIC execution cycle, from microarchitecture and design implementation through design fixes, sign-off checks, and silicon bring-up.
Work with silicon solution teams to triage silicon or programming bugs in the lab.