ASIC Design Engineer

Broadcom • Fort Collins, CO

4d • Onsite

About The Position

Join Broadcom’s Custom Silicon Design Team within the ASIC Products Division in Fort Collins, Colorado, developing custom CMOS ASICs for AI, cellular, networking, computing, and storage products. This design engineering role focuses on physical implementation of high-performance ASICs, including designs with multi-hundred-million-gate complexity using 3 nm and smaller process nodes at speeds exceeding 1 GHz. The work spans concept through production and provides exposure to advanced design methodologies and collaboration with senior engineers across disciplines.

The engineer will contribute to physical design implementation and related activities such as floorplanning, placement, clock tree synthesis, routing, timing closure, physical verification, timing analysis, power planning, IR/EM checks, and post-route optimization. The role also involves cross-functional design integration and signoff, EDA tools, design-flow improvement, automation, and deep sub-micron methodology development. It offers exposure to the complete ASIC design cycle from RTL to GDSII and silicon bring-up, as well as technical discussions and design reviews with customers and internal stakeholders.

Requirements

• Bachelor’s or master’s degree in Electrical Engineering or Computer Engineering.
• Solid understanding of VLSI design, CMOS logic, and digital circuit fundamentals.
• Familiarity with ASIC physical design concepts, including placement, routing, and timing.
• Strong analytical and debugging skills, with the ability to quickly learn new tools and flows.
• Proficiency in UNIX/Linux environments.
• Working knowledge of TCL.
• Excellent communication, collaboration, and problem-solving abilities.
• Ability to work effectively with cross-functional and global teams.
• Highly motivated, detail-oriented, and eager to learn in a fast-paced R&D environment.
• Strong engineering judgment, ownership, and accountability.

Nice To Haves

• Familiarity with Python or Perl.
• Exposure to EDA tools such as Cadence Innovus, Synopsys ICC2, or PrimeTime.

Responsibilities

• Contribute to physical design implementation of large-scale ASICs with multi-hundred-million-gate complexity.
• Support floorplanning, placement, clock tree synthesis, routing, timing closure, and physical verification (DRC/LVS).
• Collaborate with cross-functional teams on block-level integration, timing analysis, and design signoff.
• Use commercial and in-house EDA tools for design, implementation, and verification.
• Contribute to design-flow improvements, automation, and deep sub-micron methodology development.
• Assist with timing analysis, power planning, IR/EM checks, and post-route optimization.
• Gain exposure to the complete ASIC design cycle from RTL to GDSII and silicon bring-up.
• Interface with customers and internal stakeholders in technical discussions and design reviews.

Benefits

• Discretionary annual bonus.
• Competitive new-hire equity grant and annual equity awards, subject to applicable plan documents and award agreements.
• Medical, dental, and vision plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program (ESPP).
• Employee Assistance Program (EAP).
• Company-paid holidays.
• Paid sick leave and vacation time.
• Paid Family Leave and other leaves of absence in accordance with applicable laws.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level