ASIC Design - Floorplan Engineer

Broadcom • Fort Collins, CO

6d

About The Position

Join Broadcom’s Custom Silicon Design Team within its ASIC Products Division in Fort Collins, Colorado. The team develops custom CMOS ASICs for AI, cellular, networking, computing, and storage products. This role focuses on chip-level physical architecture and integration for advanced ASICs operating at speeds exceeding 1 GHz, from concept through production. It offers hands-on work with 3 nm and smaller process nodes, defining and optimizing die layout, including partitioning, hierarchy, and placement of major functional blocks, memories, and I/O structures for AI, computing, and networking SoCs.

The engineer will work with RTL, timing, packaging, block owners, integration teams, customers, and other partners to meet performance, power, and area targets and deliver signoff-quality results. The role also contributes to advanced-process design-flow automation and methodology development, and provides technical leadership and guidance.

Requirements

• BS in Electrical or Computer Engineering with 12+ years of relevant experience, or MS in Electrical or Computer Engineering with 10+ years of relevant experience.
• Strong foundation in VLSI design principles and ASIC physical design fundamentals.
• In-depth experience with floorplanning, die partitioning, and hierarchical design.
• Working knowledge of PLLs, clock networks, power delivery, and timing-critical structures.
• Proven ability to drive PPA optimization through layout and planning strategies.
• Strong experience with TCL scripting and Linux environments.
• Excellent communication, organizational, and problem-solving skills.
• Ability to work effectively with customers and cross-functional teams across global sites and time zones.
• Ability to organize and present large data sets and manage multiple priorities efficiently.
• Independent judgment and strong engineering insight in defining methods, techniques, and evaluation criteria.

Nice To Haves

• Proficiency in Python, Perl, or Ruby.
• Experience with Cadence or equivalent physical design tools.

Responsibilities

• Define and optimize top-level floorplan architecture, including die-size estimation, hierarchy definition, and partitioning.
• Drive macro placement, power-grid design, clock-distribution planning, pin placement, and feedthrough optimization.
• Collaborate with RTL, timing, and packaging teams to balance performance, power, and area targets.
• Lead top-level timing closure, congestion analysis, and ECO implementation to ensure tapeout readiness.
• Coordinate with block owners and integration teams for block-level to top-level convergence.
• Support cross-functional design integration and provide guidance and technical support to internal and external partners.
• Apply knowledge of block PnR, timing closure, physical verification, and IR/EM analysis to achieve signoff-quality results.
• Contribute to design-flow automation and methodology development for advanced process technologies.
• Provide technical leadership, mentor others, and lead execution of new initiatives.

Benefits

• Discretionary annual bonus.
• Competitive new-hire equity grant and opportunity for annual equity awards.
• Medical, dental, and vision plans.
• 401(K) participation with company matching.
• Employee Stock Purchase Program (ESPP).
• Employee Assistance Program (EAP).
• Company-paid holidays.
• Paid sick leave and vacation time.
• Paid Family Leave and other leaves of absence in accordance with applicable laws.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior