ASIC Design Engineer
About The Position
Join Broadcom’s Custom Silicon Design Team within its ASIC Products Division in Fort Collins, Colorado. The role focuses on physical implementation of high-performance custom CMOS ASICs for AI, cellular, networking, computing, and storage products. The engineer will work on large-scale designs using advanced process nodes, including 3 nm and smaller, and contribute across the design lifecycle from concept through production, with exposure to RTL-to-GDSII implementation and silicon bring-up. The position involves hands-on work with design methodologies and collaboration with engineers across multiple disciplines, customers, and internal stakeholders. The role includes physical design implementation, block-level integration, timing analysis and closure, physical verification, design signoff, and optimization. It also supports improvements to design flows, automation, and deep sub-micron methodologies, using commercial and in-house EDA tools.
Requirements
- Bachelor’s or master’s degree in Electrical Engineering or Computer Engineering.
- Solid understanding of VLSI design, CMOS logic, and digital circuit fundamentals.
- Familiarity with ASIC physical design concepts such as placement, routing, and timing.
- Strong analytical and debugging skills, with the ability to quickly learn new tools and flows.
- Proficiency in UNIX/Linux environments.
- Working knowledge of TCL.
- Excellent communication, collaboration, and problem-solving abilities.
- Ability to work effectively with cross-functional and global teams.
- Highly motivated, detail-oriented, and eager to learn in a fast-paced R&D environment.
- Strong engineering judgment, ownership, and accountability.
Nice To Haves
- Familiarity with Python or Perl.
- Exposure to EDA tools such as Cadence Innovus, Synopsys ICC2, or PrimeTime.
Responsibilities
- Contribute to physical design implementation of large-scale ASICs with multi-hundred-million-gate complexity.
- Support floorplanning, placement, clock tree synthesis, routing, timing closure, and physical verification, including DRC/LVS.
- Collaborate with cross-functional teams on block-level integration, timing analysis, and design signoff.
- Use commercial and in-house EDA tools for design, implementation, and verification.
- Contribute to design flow improvements, automation, and deep sub-micron methodology development.
- Assist with timing analysis, power planning, IR/EM checks, and post-route optimization.
- Gain exposure to the complete ASIC design cycle, from RTL to GDSII and silicon bring-up.
- Interface with customers and internal stakeholders in technical discussions and design reviews.
Benefits
- Discretionary annual bonus.
- Competitive new-hire equity grant and annual equity awards, subject to applicable plan documents and award agreements.
- Medical, dental, and vision plans.
- 401(k) participation with company matching.
- Employee Stock Purchase Program (ESPP).
- Employee Assistance Program (EAP).
- Company-paid holidays.
- Paid sick leave and vacation time.
- Paid Family Leave and other leaves of absence in accordance with applicable laws.
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What This Job Offers
Job Type
Full-time
Career Level
Entry Level
