Senior ASIC Design Engineer – Clocks IP

NVIDIA•Austin, TX

4d•$136,000 - $264,500•Hybrid

About The Position

NVIDIA’s clocks team designs GPU and CPU clocking and collaborates with front-end design, floor-planning, back-end, software, verification, timing, DFT, and silicon solution teams. The Senior ASIC Design Engineer will architect clock domains that satisfy functional, physical, and testing requirements; develop clocking RTL and topologies; and contribute throughout the ASIC execution cycle, from microarchitecture and implementation through sign-off and silicon bring-up.

Requirements

Bachelor’s degree in Electrical Engineering or equivalent experience.
At least 3 years of relevant work experience.
Deep understanding of logic optimization techniques and PPA trade-offs.
Excellent interpersonal skills and ability to collaborate with multiple teams.
Experience with RTL design using Verilog, verification, and logic synthesis.
Strong coding skills in Python or other industry-standard scripting languages.

Nice To Haves

Master’s degree.
Understanding of sub-micron silicon issues such as noise, crosstalk, and OCV effects.
Experience implementing on-chip clocking networks.
Experience with clock controllers and clock logic design.
Understanding of system-level artifacts such as power and noise.
Experience with scalable designs and architecture.
Hands-on silicon debug experience.

Responsibilities

Architect clock domains to meet functional, physical, and testing design requirements.
Design GPU or CPU clocks that satisfy architectural, design, and physical constraints.
Evaluate trade-offs across design-for-test (DFx), physical implementation, power optimization, and timing closure to improve power, performance, and area (PPA).
Innovate and implement new clocking topologies in RTL.
Collaborate with physical design and timing teams to assess clocking concerns and develop solutions for high-speed clocking.
Deliver clock RTL information to GPU, CPU, and SoC verification teams, as well as timing and DFT teams.
Participate in the end-to-end ASIC execution cycle, including microarchitecture, design implementation, design fixes, sign-off checks, and silicon bring-up.