Senior ASIC Design Engineer

Cornelis Networks, Inc. • San Jose, CA

13h • Remote

About The Position

Cornelis Networks is seeking Senior ASIC Design Engineers to develop world-class SoCs for high-performance computing, advanced data analytics, and AI interconnect solutions. The role focuses on ASIC design for high-speed data paths, packet processing, and Host Fabric Interface subsystems. Candidates with networking-domain experience, including 50G, 100G, and 400G Ethernet protocols such as TCP/IP, RDMA/RoCE, and IPSec, are particularly relevant.

This is a remote position for employees residing within the United States. The role collaborates with verification, physical design, hardware, firmware, and software teams on design coverage, timing closure, post-silicon validation, debugging, and performance and power optimization. Cornelis Networks offers a competitive compensation package that includes equity, cash, and incentives, together with health and retirement benefits.

Requirements

• B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or a related field.
• 8+ years of post-college experience in digital design.
• Proficiency in Verilog and SystemVerilog.
• Experience with RTL design for high-speed data paths or packet processing in ASICs.
• Deep understanding of Host Ethernet adapter architectures.
• Familiarity with timing closure and modern physical design methodologies.
• Proven ability in system-level debugging and root cause analysis of technical issues.
• Strong verbal and written communication skills.

Nice To Haves

• Knowledge of Ethernet architecture and networking protocols.
• Prior experience with RTL development for Ethernet host adapters and system debug.
• Expertise in multiple clock-domain designs and asynchronous interfaces.
• 5+ years of experience with scripting languages such as TCL, Python, or Perl.
• Familiarity with EDA tools such as Design Compiler, Spyglass, or PrimeTime.

Responsibilities

• Implement RTL designs using Verilog/SystemVerilog for high-speed data paths and packet processing logic.
• Collaborate with verification engineers to create block- and system-level test plans and ensure comprehensive design coverage.
• Define timing constraints for RTL blocks and work with Physical Design engineers to optimize timing closure.
• Support post-silicon validation and collaborate with hardware, firmware, and software teams to debug and resolve ASIC issues.
• Contribute to performance optimization and power-aware design strategies for Host Fabric Interface subsystems.

Benefits

• Equity, cash, and incentives as part of a competitive compensation package.
• Medical, dental, and vision coverage.
• Disability and life insurance.
• Dependent care flexible spending account.
• Accidental injury insurance.
• Pet insurance.
• Generous paid holidays.
• 401(k) with company match.
• Open Time Off (OTO) for regular full-time exempt employees.
• Sick time, bonding leave, and pregnancy disability leave.
• Potential eligibility for performance-based incentives, including an annual bonus or sales incentives, depending on role.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior