ASIC Physical Design Engineer
About The Position
The Silicon One team develops hardware platforms that support Cisco’s Switching, Routing, and Wireless products. The team carries products through full development, from design through qualification and production. As a Physical Design Engineer, you will contribute to the RTL-to-GDSII implementation of advanced semiconductor designs. You will optimize floorplanning and timing, analyze and improve backend design flows, and work across teams to help deliver high-performance networking chips. The role includes hierarchical floorplanning, place and route, static timing analysis, power integrity, equivalence checks, clock tree synthesis strategies, timing ECO implementation, and sign-off across multi-mode, multi-corner scenarios. You will also evaluate timing methodologies and tools across technologies and design types, and contribute to STA automation.
Requirements
- Bachelor’s degree in Electrical Engineering and at least 5 years of Physical Design experience, or a Master’s degree in Electrical Engineering and at least 3 years of Physical Design experience, or a PhD in Electrical Engineering.
- Experience with RTL-to-GDSII flow and design tapeouts in 7nm, 5nm, 3nm, or smaller process technologies.
- Experience with EDA tools such as Innovus, Tempus/Primetime, Redhawk/Voltus, or Calibre.
Nice To Haves
- Experience with hierarchical design, timing closure, physical convergence, and power integrity analysis.
- Experience with static timing analysis concepts, defining timing constraints and exceptions, and defining corners and voltage.
- Experience with Python, TCL, or Perl programming.
Responsibilities
- Drive RTL-to-GDSII implementation, including hierarchical floorplanning, place and route, static timing analysis, power integrity, and equivalence checks, with a focus on performance and die-size optimization.
- Analyze existing tool flows and methodologies, identify efficiency gaps, and implement incremental or transformative enhancements.
- Collaborate with RTL, DFT, implementation, EDA vendors, and tool/flow teams to enable design methodology improvements.
- Guide clock tree synthesis strategies and provide actionable feedback to implementation teams.
- Execute STA setup, convergence methodologies, and sign-off processes across multi-mode, multi-corner scenarios.
- Implement Timing ECOs using Tweaker/Primetime-based flows and contribute to STA methodology automation.
- Evaluate timing methodologies and tools across different technologies and design types.
Benefits
- Medical insurance
- Dental insurance
- Vision insurance
- 401(k) plan with Cisco matching contribution
- Paid parental leave
- Short- and long-term disability coverage
- Basic life insurance
- Paid holidays and a floating holiday for non-exempt employees
- Birthday day off, year-end holiday shutdown, and personal wellness days
- Paid vacation or flexible vacation time off, depending on employee classification
- Paid sick time
- Additional paid time away may be requested for critical or emergency family issues
- Optional paid volunteer days
- Annual bonuses may be available for non-sales roles, subject to Cisco policies
- Cisco restricted stock unit grants may be available, subject to eligibility and continued employment
Stand Out From the Crowd
Upload your resume and get instant feedback on how well it matches this job.
What This Job Offers
Job Type
Full-time
Career Level
Mid Level
