ASIC Physical Design Engineer
About The Position
The Physical Design Engineer will work on the Silicon One team, which develops hardware platforms and silicon for Cisco’s Switching, Routing, and Wireless products. This role contributes to full RTL-to-GDSII implementation for advanced semiconductor nodes, optimizing floor planning and timing, improving backend design flows, and collaborating with cross-functional teams to deliver high-performance networking chips. The engineer will drive implementation and timing closure activities, evaluate timing methodologies and tools across technologies and design types, and contribute to sign-off and automation approaches. The position works with RTL, DFT, implementation, EDA vendors, and tool and flow teams.
Requirements
- Bachelor’s degree in Electrical Engineering and 5+ years of Physical Design experience, or a Master’s degree in Electrical Engineering and 3+ years of Physical Design experience, or a PhD in Electrical Engineering and 0+ years of Physical Design experience.
- Experience with RTL2GDSII flow and design tapeouts in 7nm, 5nm, 3nm, or below process technologies.
- Experience working with EDA tools such as Innovus, Tempus/Primetime, Redhawk/Voltus, or Calibre.
Nice To Haves
- Experience with hierarchical design, timing closure, physical convergence, and power integrity analysis.
- Experience with static timing analysis concepts, defining timing constraints and exceptions, and corners/voltage definitions.
- Experience with Python, TCL, or Perl programming.
Responsibilities
- Drive RTL-to-GDSII implementation, including hierarchical floorplanning, place and route, static timing analysis, power integrity, and equivalence checks, focusing on performance and die-size optimization.
- Analyze existing tool flows and methodologies, identify efficiency gaps, and implement incremental or transformative enhancements.
- Collaborate with RTL, DFT, implementation, EDA vendors, and tool/flow teams to enable design methodology improvements.
- Guide clock tree synthesis (CTS) strategies and provide actionable feedback to implementation teams.
- Execute STA setup, convergence methodologies, and sign-off processes across multi-mode, multi-corner scenarios.
- Complete Timing ECO implementation using Tweaker/Primetime-based flows and contribute to STA methodology automation.
- Evaluate multiple timing methodologies and tools across different technologies and design types.
Benefits
- Medical insurance
- Dental insurance
- Vision insurance
- 401(k) plan with Cisco matching contribution
- Paid parental leave
- Short- and long-term disability coverage
- Basic life insurance
- Paid holidays
- Floating holiday for non-exempt employees
- Paid day off for employee’s birthday
- Paid year-end holiday shutdown
- Paid personal wellness days
- Paid vacation time for non-exempt employees
- Flexible vacation time off program for eligible exempt employees
- Sick time off
- Additional paid time away may be requested for critical or emergency family issues
- Optional paid volunteer days
- Annual bonuses for eligible non-sales roles
- Employees may be eligible for Cisco restricted stock unit grants
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What This Job Offers
Job Type
Full-time
Career Level
Senior
