Senior ASIC Design Verification Infrastructure and Tools Engineer – GPU
About The Position
NVIDIA is seeking a senior engineer to advance the systems that qualify, integrate, and deliver complex ASIC IP across multiple products. The role is suited to an RTL compose or pre-silicon verification engineer interested in infrastructure, automation, continuous integration, metrics, and efficiency tooling. The high-speed IO infrastructure team develops integration automation, pre-submit qualification, build and verification infrastructure, operational metrics, and debug workflows. The engineer will collaborate across build, verification, firmware, methodology, and infrastructure teams to make engineering systems faster, more reliable, and easier to understand. The role also involves applying AI efficiency tools effectively.
Requirements
- BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
- At least 5 years of relevant industry experience.
- Strong understanding of ASIC development workflows, including builds, simulation, regressions, debug, integration, and qualification.
- Experience with verification methodology such as UVM or similar.
- Strong working knowledge of Verilog/SystemVerilog, including RTL development or pre-silicon verification/debug experience.
- Exposure to industry simulation and debug tools such as VCS, Verdi, Xcelium, or similar.
- Strong programming skills in Python, Perl, or another scripting or systems programming language.
- Experience with SystemVerilog and object-oriented verification environments.
- Strong root-cause analysis skills, especially for intermittent or difficult-to-isolate infrastructure failures.
- Ability to independently investigate loosely defined technical problems across domains and deliver a working solution.
Nice To Haves
- Passion for infrastructure, automation, and driving efficiency gains beyond core RTL or DV tasks.
- Curiosity about complex systems and a track record of solving problems across build, verification, tooling, and infrastructure boundaries.
- Practical experience applying AI tools to engineering workflows, including debug automation, summarization, or tool-assisted development.
- Engineering habits centered on clear data: defining useful signals, using them in technical discussions, and optimizing systems against them.
- Experience providing ASIC IP for several products, projects, or SoCs simultaneously.
Responsibilities
- Apply practical AI workflows to debugging, run triage, summarization, documentation, and workflow automation.
- Build and improve high-speed IO integration, build, simulation, and pre-submit qualification flows for large ASIC IP development.
- Improve CI reliability, turnaround time, debuggability, and scalability across distributed compute environments.
- Root-cause complex failures across development, verification, build systems, tools, infrastructure, and compute environments.
- Convert recurring integration or qualification difficulties into durable automation and process improvements.
- Define, publish, and use metrics for integration latency, flow health, failure trends, and engineering efficiency.
- Use metrics in engineering discussions to guide priorities, forecast risk, and optimize systems.
- Collaborate with ASIC designers, verification engineers, firmware engineers, methodology teams, and infrastructure partners.
- Investigate unfamiliar technical areas, understand systems end to end, and drive ambiguous problems to resolution.
Benefits
- Equity
- Benefits
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What This Job Offers
Job Type
Full-time
Career Level
Senior
