ASIC / FPGA Design Verification Engineer - (Associate or Experienced)

Boeing•El Segundo, CA
•$98,600 - $162,150•Onsite

About The Position

Boeing Space, Intelligence & Weapons Systems is hiring multiple ASIC and/or FPGA Design Verification Engineers for its Boeing Electronic Products team in El Segundo or Huntington Beach, California. The team supports ASIC, FPGA, and SoC verification across aerospace programs involving space systems, satellite technologies, NASA mission support, aviation platforms, communications systems, and related digital subsystems. The position is expected to be 100% onsite at one of the listed locations and is for first shift. The role is intended to develop adaptable verification engineers with strong technical fundamentals who progress from guided execution to independent ownership of assigned verification work. Level II engineers learn department processes, communicate proactively, and manage assigned scope. Level III engineers independently own verification scope of moderate complexity and support closure, integration, and traceability activities. Engineers contribute to simulation, debug, coverage assessment, requirements traceability, integration support, and verification closure appropriate to their experience. They are expected to build proficiency in SystemVerilog, UVM environments, tests, reusable verification infrastructure, UVC development, and broader verification methodologies. The role emphasizes communicating status, blockers, assumptions, risks, dependencies, and learning needs, while developing technical depth and collaborating with teammates who have complementary strengths. The selected candidate must be able to obtain a U.S. Security Clearance; U.S. citizenship is required, and an interim and/or final U.S. Secret Clearance is required after starting. Boeing will not sponsor applicants for employment visa status. Candidates must also satisfy the Company's Conflict of Interest assessment process. Relocation may be offered based on eligibility. Pay ranges are $98,600–$133,400 for Associate (Level 2) and $119,850–$162,150 for Experienced (Level 3), based on experience, qualifications, market, and business considerations.

Requirements

  • Ability to obtain a U.S. Security Clearance; U.S. citizenship is required, with an interim and/or final U.S. Secret Clearance required post-start.
  • Bachelor of Science degree in a listed or directly related field, including Engineering, Computer Science, Data Science, Mathematics, Physics, or Chemistry, or non-U.S. equivalent qualifications directly related to the work statement.
  • Bachelor’s degree with 2 or more years of professional engineering experience in ASIC, FPGA, or SoC design verification, or a Master’s degree with related verification project or coursework experience.
  • Understanding of digital verification fundamentals.
  • Experience with SystemVerilog for simulation testbench development and RTL debugging.
  • Satisfy the Company's Conflict of Interest assessment process.
  • For the typical Level III profile, typically 5 or more years of related work experience or an equivalent combination of technical education and experience.

Nice To Haves

  • UVM experience; strongly preferred.
  • Object-oriented programming (OOP) experience; strongly preferred.
  • Coverage-driven verification exposure.
  • Requirements traceability experience.
  • Reusable UVC development exposure.
  • System-level debug exposure.
  • Strong communication and technical presentation skills.
  • Active U.S. Secret Security Clearance.
  • For Level III, a bachelor’s degree in EE, CE, or a related field and 2 or more years of ASIC, FPGA, or SoC verification experience.
  • ABET-accredited education; preferred but not required in the USA.

Responsibilities

  • Execute assigned verification tasks and progressively increase ownership.
  • Develop simulation, debug, coverage, and requirements traceability skills.
  • Contribute to SystemVerilog and UVM environments, tests, UVCs, and reusable infrastructure.
  • Support integration investigations and system-level debug activities.
  • Contribute to verification objectives, coverage assessments, and closure activities appropriate to experience level.
  • Independently own verification scope of moderate complexity at Level III.
  • Communicate status, blockers, assumptions, risks, dependencies, and learning needs proactively.
  • Support closure, integration, and traceability activities.

Benefits

  • Competitive base pay and variable compensation opportunities.
  • Eligible employees may enroll in health insurance, flexible spending accounts, health savings accounts, retirement savings plans, life and disability insurance programs, and programs providing paid and unpaid time away from work.
  • Relocation based on candidate eligibility.
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