ASIC / FPGA Digital Design Engineer – (Associate or Experienced)

Boeing•El Segundo, CA

1d•$98,600 - $162,150•Onsite

About The Position

Boeing Space, Intelligence & Weapons Systems is seeking multiple ASIC/ FPGA Digital Design Engineers, at both Associate and Experienced levels, to join the Boeing Electronic Products team. This role focuses on advanced digital subsystem development within an aerospace environment, with opportunities in El Segundo or Huntington Beach, CA. Engineers will support ASIC, FPGA, or mixed ASIC/FPGA developments, contributing to requirements, architecture, HDL development, simulation, synthesis, FPGA implementation, timing analysis, integration, troubleshooting, and verification collaboration. The work spans advanced aerospace and defense programs in space, aviation, communications, and autonomous systems, including next-generation satellites, NASA missions, Space Launch System technologies, commercial and military aircraft, and autonomous aviation technologies. The department's expertise covers a wide range of digital design activities, and engineers have opportunities to grow their careers from focused contributors to technical leaders.

Requirements

Ability to obtain a US Security Clearance for which the US Government requires US Citizenship as a condition of employment. An interim and/or final U.S. Secret Clearance Post-Start is required.
Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement
Bachelor’s degree and 2+ years of experience with years FPGA, ASIC, or SoC digital design; or a BS and completed MS degree
Experience with HDL development, simulation, debug, and synthesis
Strong digital design fundamentals (coursework in digital logic design, computer architecture, ASIC design flow, VLSI Design, etc.)
Experience troubleshooting digital systems (debugging RTL design, HDL/architecture)

Nice To Haves

Experienced, Level 3: 5+ years of related engineering experience
Bachelor’s Degree or Master's Degree in EE, Computer Engineering/Science, or related field
Active U.S. Secret Security Clearance
Requirements development and traceability experience
FPGA implementation including constraints and timing closure
Static timing analysis experience
Understanding of timing fundamentals and CDC concepts
Verification collaboration experience
High-speed interfaces, processor integration, memory subsystems, or SoC integration
Mentoring or technical leadership exposure
Familiarity with industry-standard tools and methodologies

Responsibilities

Support ASIC, FPGA, or mixed ASIC/FPGA developments depending on assignment
Contribute to requirements development, refinement, interface definition, conceptual architecture activities, and traceability efforts appropriate to role level
Develop HDL / RTL for ASIC, FPGA, and SoC systems
Compile, simulate, debug, and troubleshoot digital designs
Perform and/or support synthesis, implementation, constraints development, timing closure, and tool execution activities
Collaborate with verification teams to support simulation, debug, coverage, and integration goals
Apply timing concepts, CDC fundamentals, and integration considerations
Support broader system troubleshooting and integration activities
Communicate technical status, risks, dependencies, and tradeoffs proactively