FPGA Design Engineer (Associate, Experienced, or Senior)

Boeing•Huntsville, AL

6d•$91,800 - $185,150•Onsite

About The Position

Boeing Defense, Space & Security (BDS) is hiring for an Associate, Experienced or Lead FPGA Design Engineer to join our team in Huntsville, AL to develop, debug, and integrate processor subsystem features and interfaces in FPGA hardware for Advanced Processors. You will be working on cutting-edge technologies, supporting various domain areas such as flight command and control, air traffic control, and homeland defense. This position requires the ability to obtain a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim or final U.S. Secret clearance post-start is required.

Requirements

Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement
2 or more years' related work experience
Experience using FPGA design tools (such as: Modelsim, Xilinx Vivado or ISE, Altera Quartus, Microsemi, or similar)
Experience with Hardware Description Language (HDL) code development
Must meet U.S. export control compliance requirements. To meet U.S. export control compliance requirements, a “U.S. Person” as defined by 22 C.F.R. §120.62 is required. “U.S. Person” includes U.S. Citizen, U.S. National, lawful permanent resident, refugee, or asylee.
Ability to obtain a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim and/or final U.S. Secret Clearance Post-Start is required.

Nice To Haves

MSEE, MSCE experience
Experience with Verilog, C/C++, MATLAB/Simulink
Synopsis Synplify, Synopsis VCS, NCSim, ChipScope tool sets
Experience with Xilinx/AMD and MicroSemi/Microchip part families internal FPGA fabric and IP
FPGA design experience with tools noted above
Previous experience related to aerospace design techniques
Experience with management of Configuration Control (GitLab preferred)
Experience with Vivado and Vitis FPGA toolsets
Experience with UVM
Experience working with Versal FPGAs
Experience with troubleshooting and debugging with board-level testing and FPGA validation
Experience in FPGA life cycle (architecture, design, simulation, verification, validation, integration & test)

Responsibilities

Develop FPGA requirements, FPGA code of logic design.
Generate self-checking test bench, unit test, synthesis, timing analysis, Built-In-Test (BIT) and support of debug and system integration activities
Develop, debug, and integrate processor subsystem features and interfaces in FPGA hardware for advanced processors
Develop high-speed serial interferences inside an FPGA. (SERDES)
Collaborate with cross-functional teams including other engineering disciplines
Stay current on industry best practices and technological advancements in FPGA design and Digital Signal Processing