ASIC Design Verification Engineer

Meta•Sunnyvale, CA

14h•$178,000 - $250,000

About The Position

Meta is hiring an ASIC Design Verification Engineer within its Infrastructure organization to help build IP and System On Chip (SoC) solutions for data center applications. The engineer will work on an agile team with experienced engineers and contribute to ASIC solutions for Meta’s data center needs. The role is responsible for verification closure of a design module or subsystem, from test planning and UVM-based testbench development through verification closure. In addition to traditional simulation, the engineer will use approaches such as Formal and Emulation to help achieve bug-free designs. The role involves partnering with software, hardware, ASIC Design, Emulation, and Post-Silicon teams to support first-pass silicon success.

Requirements

Bachelor’s degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience.
8+ years of experience in IP/subsystem and/or SoC-level verification using SystemVerilog UVM/OVM methodologies and/or C/C++-based verification.
Experience leading verification of SoCs/chiplets or complex IP such as PCIe, RoCE, DDR, HBM, Ethernet, cache controllers, or Network on Chip.
Experience with EDA tools and scripting languages (Python, TCL, Perl, or Shell) used to build tools and flows for verification environments.

Nice To Haves

Experience in one or more of SV Assertions, Formal, or Emulation, in addition to functional verification.
Experience verifying ARM/RISC-V-based subsystems or SoCs.
Experience working across and building relationships with cross-functional design, model, and emulation teams.
Experience with micro-architectural performance verification.
Experience with revision control systems such as Mercurial (Hg), Git, or SVN.
Track record of first-pass success in ASIC development cycles.
Experience architecting and implementing design verification infrastructure and executing the full verification cycle.
Experience verifying data-center applications such as Video, AI/ML, and Networking designs.
Experience verifying GPU/CPU designs.
Experience developing UVM-based verification environments from scratch.

Responsibilities

Define and implement IP/SoC verification plans and build testbenches for IP, subsystem, and SoC-level verification.
Develop functional tests based on verification test plans.
Drive design verification to closure against defined test-plan, functional, and code-coverage metrics.
Debug, identify root causes of, and resolve functional design failures in partnership with the Design team.
Collaborate with Design, Model, Emulation, and Silicon Validation teams to ensure design quality meets verification and coverage goals.
Develop and drive continuous improvements to design verification using industry methodologies, tools, and technologies.