ASIC Design Verification Engineer - Slingshot

Hewlett Packard Enterprise • Fort Collins, CO

1d • $109,000 - $251,000 • Hybrid

About The Position

Hewlett Packard Enterprise is hiring an ASIC Design Verification Engineer for its Slingshot team, which develops an interconnect used in large-scale HPC and AI systems. The engineer will work with architects, logic designers, and verification engineers on switch and NIC ASICs for a future generation of Slingshot. The role owns block verification from test planning through sign-off, with opportunities to deepen technical expertise and apply agentic AI workflows to engineering problems.

The role covers all phases of pre-silicon design verification, including methodology, test-plan and testbench development, coverage closure, and sign-off reviews. It is hybrid, requiring an average of two days per week in an HPE office. The engineer will work independently as part of a project team that includes VLSI engineers and internal and outsourced development partners, and will provide guidance and mentoring to less experienced staff.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
• At least 5 years of experience in VLSI design, verification, or implementation.
• Strong knowledge of SystemVerilog and OVM or UVM methodologies.
• Strong knowledge of programming and scripting languages, hardware description languages, and electronic design automation (EDA) tools.
• Strong analytical and problem-solving skills.
• Ability to be self-directed in a distributed team environment.
• Strong written and verbal communication skills and mastery of English.

Nice To Haves

• Experience verifying high-speed networking, switching, or NIC ASICs.
• Experience with agentic AI coding tools and workflows applied to verification.
• Experience with Python, Perl, Tcl, or another scripting language in Linux development environments.
• Experience working as part of a geographically distributed team.

Responsibilities

• Follow and improve the team's design verification methodology.
• Develop SystemVerilog and UVM testbench components, including bus functional models that drive and monitor stimulus.
• Plan and implement block-level scoreboards and checkers to verify functional behavior.
• Write and analyze functional coverage to find verification gaps and drive coverage closure.
• Triage regression failures, identify logic bugs, and drive bug closure.
• Apply scripting, automation, and AI-assisted and agentic tools to improve the speed and quality of the verification process.
• Work with designers, architects, and project leads on design status, verification progress, and issue resolution.
• Work independently as a member of a project team that includes other VLSI engineers and internal and outsourced development partners.
• Provide guidance and mentoring to less experienced staff members.

Benefits

• A comprehensive suite of benefits supporting physical, financial, and emotional wellbeing.
• Career development programs to help employees pursue career goals.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior