Senior ASIC Design Verification Engineer
About The Position
The Senior ASIC Design Verification Engineer will help develop Cisco data center solutions by defining, designing, and verifying ASICs and ASIC subsystems for Cisco platforms. The role contributes to multidisciplinary engineering teams working toward product power, performance, and area goals, and owns complex or multiple functional areas. The engineer defines verification methodologies for advanced design architectures, creates reusable code, and leads verification efforts across block, cluster, and chip levels. Responsibilities include building and maintaining DV infrastructure, implementing test plans and tests using constraint-random and directed stimulus, ensuring code and functional coverage, qualifying RTL through gate-level simulations with timing annotation, supporting emulation, debugging issues across ASIC, software, and systems, and assisting with lab bring-up and post-silicon validation.
Requirements
- Bachelor's degree in Computer, Electrical, or Electronics Engineering and at least 7 years of relevant technical experience, or a master's degree and at least 4 years of relevant technical experience focused on ASIC design and verification.
- Experience with object-oriented programming concepts and SystemVerilog or UVM methodology.
- Experience leading verification teams or project assignments.
- Experience with scripting using Perl and/or Python.
Nice To Haves
- Experience with forwarding logic, parsers, or P4.
- Experience using emulation platforms such as Veloce, Palladium, Zebu, or HAPS.
- Knowledge of formal verification tools such as IEV or VC Formal.
- Domain knowledge in one or more protocols such as PCIe, CXL, Ethernet, RDMA, DDR, or TCP.
Responsibilities
- Drive the definition, architecture, and design of high-performance ASICs while owning complex or multiple functional areas.
- Define verification methodologies for advanced design architectures and develop reusable code for future projects.
- Lead design verification by resolving block-level issues, participating in cluster- and chip-level issue resolution, and driving reviews to identify architectural concerns.
- Architect, develop, and maintain cluster- and top-level design verification environment infrastructure.
- Build design verification environments from scratch for cluster and chip levels.
- Develop, implement, and enhance test plans and tests for cluster and chip verification using constraint-random and directed stimulus.
- Implement and review code and functional coverage to ensure comprehensive verification coverage.
- Qualify RTL designs by running gate-level simulations with timing annotation on netlists.
- Support design testing in emulation environments.
- Debug ASIC-, software-, and systems-level issues and assist with lab bring-up and post-silicon validation.
Benefits
- Medical, dental, and vision insurance.
- 401(k) plan with Cisco matching contribution.
- Paid parental leave.
- Short- and long-term disability coverage.
- Basic life insurance.
- Eligible employees may receive Cisco restricted stock unit grants, subject to continued employment and vesting terms.
- Paid holidays and a floating holiday for non-exempt employees.
- Paid birthday day off, year-end holiday shutdown, and personal wellness days.
- Paid vacation or flexible vacation time off, depending on employee classification.
- Sick time off and carryover of unused sick time, subject to policy.
- Additional paid time away may be requested for critical or emergency family issues.
- Optional paid volunteer days.
- Annual bonuses for eligible non-sales employees, subject to Cisco policies.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
