Senior ASIC Design Verification Engineer

Cisco•San Jose, CA

About The Position

The Senior ASIC Design Verification Engineer will develop Cisco data center solutions by defining, designing, and verifying ASICs and ASIC subsystems for Cisco platforms. The role contributes to multidisciplinary engineering teams working toward product power, performance, and area goals, and owns complex or multiple functional areas. The engineer will define verification methodologies and develop reusable code, lead block-level verification and participate in cluster- and chip-level issue resolution, and architect and maintain cluster- and top-level verification infrastructure. Responsibilities also include building verification environments, developing test plans and tests using constraint-random and directed stimulus, implementing and reviewing coverage, qualifying RTL through gate-level simulations with timing annotation, supporting emulation, debugging across ASIC, software, and system levels, and assisting with lab bring-up and post-silicon validation.

Requirements

Bachelor’s degree in Computer, Electrical, or Electronics Engineering and 7+ years of relevant technical experience, or a master’s degree and 4+ years of relevant technical experience focused on ASIC design and verification.
Experience with object-oriented programming concepts and SystemVerilog or UVM methodology.
Experience leading verification teams, assignments, or projects.
Experience with scripting using Perl and/or Python.

Nice To Haves

Experience with forwarding logic, parsers, or P4.
Experience using emulation platforms such as Veloce, Palladium, Zebu, or HAPS.
Knowledge of formal verification tools such as IEV or VC Formal.
Domain knowledge in one or more protocols such as PCIe, CXL, Ethernet, RDMA, DDR, or TCP.

Responsibilities

Drive the definition, architecture, and design of high-performance ASICs while owning complex or multiple functional areas.
Define new verification methodologies to support advanced design architectures and develop reusable code for future projects.
Lead design verification by resolving block-level issues, participating in cluster- and chip-level issue resolution, and driving reviews to identify architectural concerns.
Architect, develop, and maintain cluster- and top-level design verification environment infrastructure.
Build design verification environments from scratch for cluster and chip levels.
Develop, implement, and enhance test plans and tests for cluster and chip verification using constraint-random and directed stimulus.
Ensure comprehensive verification coverage through code and functional coverage implementation and review.
Qualify RTL designs by running gate-level simulations with timing annotation on netlists.
Support design testing in emulation environments.
Debug issues at ASIC, software, and systems levels and help with lab bring-up and post-silicon validation.

Benefits

Medical, dental, and vision insurance, subject to plan eligibility.
401(k) plan with Cisco matching contribution.
Paid parental leave.
Short- and long-term disability coverage.
Basic life insurance.
Paid holidays and a floating holiday for non-exempt employees.
Paid day off for the employee’s birthday.
Paid year-end holiday shutdown.
Paid personal wellness days.
Paid vacation or flexible vacation time off, depending on employee classification and subject to applicable policies.
Sick time off, including carryover of unused sick time subject to the stated limits.
Additional paid time away may be requested for critical or emergency family issues.
Optional paid volunteer days.
Annual bonuses may be available for non-sales roles, subject to Cisco policies.
Employees may be eligible for Cisco restricted stock unit grants.