ASIC Verification Engineer

Amentum•Crane, IN

5d•$85,000 - $100,000

About The Position

Amentum is seeking a Computer Engineer to support verification of ASICs and/or FPGAs for high-reliability and security-focused systems for Department of War customers. The engineer will develop and execute verification plans, build and maintain test environments, analyze results, and help ensure designs are free of functional flaws and security-relevant weaknesses. The position also supports automation of EDA tool flows and regression activities.

Requirements

Bachelor’s or graduate degree in Computer Engineering or Electrical Engineering.
1–5 years of experience.
SystemVerilog; familiarity with VHDL is beneficial.
Knowledge of digital design fundamentals and RTL concepts.
Experience with directed and constrained-random verification.
Experience with SystemVerilog Assertions (SVA) or assertion-based verification.
Experience with functional and code coverage analysis.
Ability to debug using waveforms and simulation logs.
Scripting experience in Python, Tcl, Bash, or similar languages.
Familiarity with common digital interfaces and subsystem concepts such as UART, SPI, I2C, MIPI, LVDS, and DMA.
Experience with EDA tools from Siemens, Cadence, Synopsys, or similar vendors.
Understanding of ASIC design and verification flow.
Ability to obtain and maintain DoD Secret Clearance; US citizenship is required to obtain a US secret clearance.

Nice To Haves

Active Secret Clearance.
Universal Verification Methodology (UVM).
ASIC verification methodologies and testbench creation.
Experience with formal verification methods.
Familiarity with logic equivalence checking (LEC).
Exposure to clock-domain crossing (CDC) or reset-domain crossing (RDC) analysis.
Knowledge of hardware security verification principles.
Experience with DFT or production test concepts, including ATPG vectors.
Familiarity with Automated Test Equipment (ATE) workflows.
Understanding of STIL/WGL vector syntax.
Experience debugging simulated versus measured waveform discrepancies.
Familiarity with layout versus schematic (LVS), design rule check (DRC), and broader ASIC signoff activities.

Responsibilities

Perform verification of ASICs and/or FPGAs for high-reliability and security-focused applications.
Develop verification plans based on design requirements and architecture documentation.
Build and maintain SystemVerilog/UVM testbenches and reusable verification components.
Create directed and constrained-random tests to validate functionality and corner cases.
Develop assertions, drivers, monitors, predictors, scoreboards, checkers, and coverage models.
Execute simulations and regression test suites; analyze and debug failures.
Review waveforms, logs, and coverage data to identify root causes and drive closure.
Collaborate with RTL design, integration, and other engineering teams to resolve issues.
Support automation of EDA flows, regressions, and reporting through scripting.
Document verification results, defects, and test status for technical reviews.