Senior ASIC Verification Engineer
About The Position
Hewlett Packard Enterprise is seeking a Senior ASIC Verification Engineer to join its networking silicon development team. HPE Networking develops advanced routers and switches, and its Networking Silicon group builds high-performance networking chips. In this role, you will work on complex ASIC/SoC blocks and subsystems as part of a fast-paced silicon development team. The position is based in Sunnyvale, California, and is described as hybrid, with an expectation of working in the office two days per week. You will lead verification efforts from test planning through coverage closure, develop and maintain UVM verification environments, debug complex designs, and collaborate across teams to deliver high-quality ASIC/SoC products.
Requirements
- At least 10 years of experience in ASIC/SoC verification, with a track record of owning verification from test plan through coverage closure.
- Strong expertise in SystemVerilog and UVM methodology, including developing verification environments from scratch.
- Deep understanding of randomization, constraints, functional coverage, and assertions (SVA).
- Hands-on experience in test planning, coverage analysis, and debugging complex SoC designs.
- Proficiency with industry-standard simulation tools such as Cadence Xcelium, Synopsys VCS, or Mentor Questa, and waveform debugging.
Nice To Haves
- Experience verifying networking ASICs or router datapath/control blocks, such as packet processing, forwarding engines, or fabric interfaces.
- Familiarity with high-speed interconnects, buffers, or scheduling pipelines in large networking SoCs.
- Exposure to emulation environments, hardware acceleration, or traffic-model integration.
- Knowledge of coverage analytics, regression dashboards, and continuous-integration flows such as Jenkins.
- Understanding of low-power (UPF) or formal verification methodologies.
- Experience with post-silicon bring-up and debug.
- Familiarity with emulation environments and debug flows.
Responsibilities
- Own and drive block-level or subsystem verification efforts from test-plan creation through comprehensive coverage closure.
- Develop, enhance, and maintain UVM verification environments, including agents, sequences, scoreboards, virtual sequences, and register models.
- Perform constraint-driven random testing and debug complex SoC designs.
- Ensure functional coverage and assertion goals are met.
- Analyze simulation results and debug waveforms to validate design functionality.
- Collaborate with cross-functional teams to identify and resolve issues and ensure high-quality ASIC/SoC deliverables.
- Drive block-level, subsystem, or full-chip verification efforts from test-plan creation through coverage closure.
Benefits
- Comprehensive benefits intended to support physical, financial, and emotional wellbeing.
- Career development programs to support professional growth and career goals.
Stand Out From the Crowd
Upload your resume and get instant feedback on how well it matches this job.
What This Job Offers
Job Type
Full-time
Career Level
Senior
Education Level
No Education Listed
