ASIC Verification Engineer, Networking

Meta•Sunnyvale, CA

2d•$178,000 - $250,000

About The Position

Meta is hiring an ASIC Design Verification, Networking Engineer within its Infrastructure organization. The role focuses on developing IP and System-on-Chip (SoC) solutions for data center applications. The engineer will own verification closure for a design module or subsystem, from test planning and UVM-based testbench development through verification closure. Verification approaches include traditional simulation as well as formal methods and emulation. The position involves partnering with full-stack software, hardware, ASIC Design, Emulation, and Post-Silicon teams to help achieve first-pass silicon success.

Requirements

Bachelor’s degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience.
8+ years of experience in IP/subsystem and/or SoC-level verification using SystemVerilog UVM/OVM methodologies and/or C/C++-based verification.
Experience in one or more networking areas alongside functional verification, such as Ethernet, 400G MAC, NIC, RDMA, PSP, RoCE, or congestion control.
Experience architecting and implementing design verification infrastructure and executing the full verification cycle.
Proficiency in scripting languages such as Python, Perl, or TCL to build tools and workflows for verification environments.
Experience debugging and resolving complex verification challenges in IP or SoC designs.
Experience collaborating with cross-functional teams such as Design, Emulation, and Silicon Validation to drive verification milestones.

Nice To Haves

Experience with IP or integration verification of high-speed interfaces such as Ethernet, PCIe, DDR, or HBM.
Experience working across and building relationships with cross-functional Design, Model, and Emulation teams.
Experience verifying ARM- or RISC-V-based subsystems or SoCs.
Experience developing fully automated flows and scripts for data exploration, analysis, and performance verification.

Responsibilities

Define and implement IP/SoC verification plans and build testbenches for IP, subsystem, and SoC-level verification.
Develop functional tests based on the verification test plan.
Drive design verification to closure against defined verification metrics, including functional and code coverage.
Debug, root-cause, and resolve functional design failures in partnership with the Design team.
Collaborate with Design, Model, Emulation, and Silicon Validation teams to ensure design quality meets verification and coverage goals.
Develop and drive continuous design verification improvements using current industry methodologies, tools, and technologies.