Senior ASIC Verification Engineer
About The Position
Cornelis Networks is hiring a Senior ASIC Verification Engineer to verify advanced SoCs for high-performance computing, high-performance data analytics, and artificial intelligence interconnect solutions. As a hands-on member of the ASIC leadership team, this engineer will lead verification closure across projects, including design modules, subsystems, and SoCs. The role covers verification strategy and planning, UVM testbench development, functional testing, regression, and coverage closure, with collaboration across ASIC design, emulation, system hardware, software, and post-silicon teams to support first-pass silicon success. The position also provides day-to-day team guidance and leadership through mentoring, coaching, and counseling; promotes AI tools to improve verification productivity; and establishes and enforces coding and verification guidelines. This is a remote position for employees residing within the United States.
Requirements
- At least 8 years of experience with hands-on coding in UVM/SystemVerilog.
- Experience verifying complex SoCs with multiple clock and reset domains using VCS or equivalent simulation tools.
- Experience debugging failures to the RTL line, closing out bug fixes, and using Verdi or equivalent debug tools.
- Experience developing testbenches from the ground up.
- Experience with revision control systems such as Git or SVN.
- Bachelor’s degree in Computer Engineering, Computer Science, or Electrical Engineering.
Nice To Haves
- Master’s degree in Computer Engineering, Computer Science, or Electrical Engineering.
- At least 8 years of relevant experience in networking hardware verification.
- Proven expertise verifying 50G, 100G, or 400G Ethernet MAC/PCS protocols, TCP/IP, RDMA/RoCE, or IPSec and their application in high-speed data processing and networking.
- Experience with one or more scripting languages, such as TCL, Python, Perl, or shell scripting.
- Track record of first-pass success in ASIC and systems.
- Experience using AI tools to generate test plans and improve verification-process and team productivity.
Responsibilities
- Define the overall SoC-level verification strategy, technical planning, and direction.
- Enable and drive development of UVM environments to verify RTL at block, unit, and SoC levels.
- Develop and execute functional tests according to verification test plans.
- Instrument testbenches for functional and code coverage and drive coverage closure based on metrics.
- Collaborate with design, software, emulation, and silicon validation teams to ensure design quality.
- Provide day-to-day guidance and leadership to team members.
- Drive results through mentoring, coaching, and counseling.
- Educate the team in using AI tools to enhance productivity and efficiency.
- Generate and enforce coding and verification guidelines.
- Lead verification closure for projects, including design modules, subsystems, and SoCs.
Benefits
- Competitive compensation package including equity, cash, and incentives.
- Health and retirement benefits.
- Medical, dental, and vision coverage.
- Disability and life insurance.
- Dependent care flexible spending account.
- Accidental injury insurance.
- Pet insurance.
- Generous paid holidays.
- 401(k) with company match.
- Open Time Off (OTO) for regular full-time exempt employees.
- Sick time.
- Bonding leave.
- Pregnancy disability leave.
- Depending on the role, eligibility for performance-based incentives, including an annual bonus or sales incentives.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
