Lead ASIC Verification Engineer

General Dynamics Mission Systems, Inc•San Jose, CA

1d•$173,032 - $190,000

About The Position

As a Lead ASIC Verification Engineer for the Bitttercloud II program at Idaho Scientific, a business segment within General Dynamics Mission Systems, you will support a cross-functional team designing and architecting embedded security technologies to protect U.S. defense systems from cyber exploitation, physical attacks, reverse engineering, and supply-chain compromise. The team delivers secure processors, anti-tamper architectures, cryptographic IP, and integrated firmware and software solutions designed to meet government cybersecurity and survivability requirements. The role leads verification at the block, subsystem, and full-chip levels. It includes developing verification plans and reusable SystemVerilog/UVM environments, maintaining requirements traceability, executing simulation and other verification activities, investigating failures, and presenting verification status and risks. The Lead Engineer also provides technical direction and mentoring, supports program planning and vendor oversight as needed, and improves verification processes and automation. Approved AI-enabled tools may be used when they provide clear engineering value and protect sensitive information. The position requires a relevant bachelor’s degree and at least 10 years of experience, or a master’s degree and at least 8 years of experience. A Department of Defense Secret clearance must be obtainable within a reasonable time, and U.S. citizenship is required. The stated annual salary range is USD $173,032 to $190,000; actual pay may vary based on experience and other factors. The posting remains open until the position is filled.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related science, engineering, or mathematics field and at least 10 years of relevant experience; or a master's degree and at least 8 years of relevant experience.
Department of Defense Secret security clearance obtainable within a reasonable time; selected applicants will undergo a U.S. Government security investigation and must meet eligibility requirements for classified access.
U.S. citizenship is required.
Strong knowledge of ASIC and SoC verification processes.
Strong proficiency in SystemVerilog, UVM, assertions, coverage, and regression testing.
Experience developing reusable testbench components and register models.
Strong understanding of RTL, digital logic, interfaces, clocks, and resets.
Ability to convert requirements into measurable verification objectives and tests.
Experience debugging simulations and determining root causes.
Experience with scripting languages such as Perl, Tcl, Bash, and Python.
Experience with ASIC simulation and debug tools such as VCS, Verdi, Questa, or equivalent tools.
Experience with Linux, version control, and automated regression environments.
Ability to communicate technical results clearly to varied audiences.
Ability to lead multiple activities while maintaining quality and schedule.
Strong technical judgment, mentoring, and problem-solving skills.

Nice To Haves

Experience with formal verification, CDC/RDC analysis, or low-power verification.
Experience with emulation, silicon bring-up, or post-silicon validation.
Experience verifying third-party IP and complex interfaces.
Experience working in an Agile development environment.
Experience with vendor oversight, proposals, estimates, or program controls.

Responsibilities

Lead ASIC verification at the block, subsystem, and full-chip levels.
Develop verification plans, schedules, coverage goals, and completion criteria.
Build reusable SystemVerilog/UVM test environments and verification components.
Maintain traceability from requirements through test results and defect closure.
Plan and execute simulation, regression, formal verification, and emulation activities.
Drive coverage and regression results toward predetermined completion goals.
Lead failure investigation, root-cause analysis, and corrective-action verification.
Verify third-party and custom IP for functional and integration compliance.
Provide feedback to design and architecture teams on issues affecting verification.
Identify verification risks and develop practical mitigation plans.
Present verification status, evidence, risks, and recommendations at technical reviews.
Produce clear, accurate verification plans, procedures, and reports.
Improve verification processes, automation, metrics, and reusable assets.
Provide technical direction and mentoring to verification engineers.
Support vendor oversight, proposals, estimates, and program planning as needed.
Use approved AI-enabled tools when they provide clear engineering value and protect sensitive information.