Senior ASIC Design Verification Engineer - Slingshot

Hewlett Packard Enterprise•Bloomington, WI

2d•Hybrid

About The Position

Hewlett Packard Enterprise is hiring a Senior ASIC Design Verification Engineer to work on HPE Slingshot, an interconnect used in large high-performance computing and AI systems. The engineer will work with architects, logic designers, and verification engineers on future-generation switch and NIC ASICs. The role owns significant verification scope, sets technical direction for a block or subsystem, and contributes to the team's use of agentic AI workflows. The position is responsible for all phases of pre-silicon design verification, including methodology, test planning and testbench development, coverage closure, and sign-off reviews. It also includes mentoring less experienced staff and influencing verification methodology and technical direction. The role is hybrid, with an average requirement of two days per week in an HPE office.

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
10+ years of experience in VLSI design, verification, or implementation.
Expert-level knowledge of SystemVerilog and OVM or UVM methodologies.
Expert-level knowledge of programming and scripting languages, hardware description languages, electronic design automation (EDA), and/or FPGA tools.
Expert-level analytical and problem-solving skills.
Ability to excel in a distributed team environment.
Executive-level written and verbal communication skills and mastery of English.

Nice To Haves

Experience verifying high-speed networking, switching, or NIC ASICs.
Experience with agentic AI coding tools and workflows applied to verification.
Experience with Python, Perl, Tcl, or another scripting language in Linux development environments.
Experience working as part of a geographically distributed team.

Responsibilities

Follow and help define the team's design verification methodology.
Develop SystemVerilog and UVM testbench components, including bus functional models that drive and monitor stimulus.
Plan and implement block- and integration-level scoreboards and checkers to verify functional behavior.
Write and analyze functional coverage and provide input to block-level milestones.
Triage regression failures, identify logic bugs, and drive bug closure.
Apply scripting, automation, and AI-assisted and agentic tools to improve the speed and quality of verification.
Guide and mentor less experienced staff, setting an example of VLSI design and development innovation and excellence.
Participate in and provide input on the process for selecting future technical leaders.
Drive VLSI innovation and integration of new technologies into projects and design-organization activities.
Participate in all phases of pre-silicon design verification, including methodology, test-plan and testbench development, coverage closure, and sign-off reviews.