Staff Engineer, ASIC Digital Design

Micron•Minneapolis, MN
•$150,000 - $256,000

About The Position

As a Staff Digital Design Engineer on Micron’s ASIC logic design team, you will help design next-generation internally developed ASICs and controller IP. The role focuses on translating architectural and product requirements into microarchitecture specifications and robust hardware implementations, with attention to performance, power, area, timing, and testability. Designs interact with custom analog circuits, third-party IP, and SystemVerilog blocks for Micron’s technology and product portfolio. The position covers RTL development for DRAM, NAND, and SSD controllers and systems, as well as simulation, synthesis, timing closure, formal verification, gate-level validation, chip bring-up, and lab validation. You will collaborate with Design Verification, Analog Design, Synthesis, and Physical Design teams; develop HDL circuit models; and provide technical leadership through design reviews, mentoring, problem solving, and engineering best practices.

Requirements

  • B.S., M.S., or Ph.D. in Electrical Engineering.
  • At least 8 years of industry experience.
  • Strong fundamental knowledge of logic design coding in SystemVerilog and verification techniques, including high-speed I/O crossings.
  • Strong written and verbal communication skills, including the ability to write and review architectural specifications and code.
  • Experience with software programming and Linux shell scripting, Python, or similar tools.
  • Understanding of analog and mixed-signal circuits and simulation, including CMOS/CML logic, PLL, DLL, and CDR.
  • Experience with DRAM interfaces, memory-system RAS (Reliability, Availability, Serviceability), and RTL development.
  • Experience with industry-standard tools for synthesis, linting, equivalency, and formal verification.
  • Willingness to learn and use AI tools in the ASIC design flow.
  • Collaborative, curious, and motivated to contribute, learn, and grow.

Nice To Haves

  • Knowledge of Generative AI in the ASIC design flow.

Responsibilities

  • Translate architectural and product requirements into detailed microarchitecture specifications and robust hardware implementations.
  • Lead digital design development involving custom analog designs, third-party IP, and SystemVerilog blocks, considering performance, power, area, timing, and testability.
  • Design and develop RTL for next-generation DRAM, NAND, and SSD controllers and systems.
  • Own and support RTL development, simulation, synthesis, timing closure, formal verification, gate-level validation, and silicon bring-up support.
  • Partner with Design Verification, Analog Design, Synthesis, and Physical Design teams.
  • Participate hands-on in chip bring-up and lab validation.
  • Develop HDL models of circuits.
  • Provide technical leadership through design reviews, mentoring, problem solving, and development of engineering best practices.

Benefits

  • Medical, dental, and vision plan options.
  • Benefits that help protect income in the event of illness or injury.
  • Paid family leave.
  • Paid time off.
  • Paid holidays.
  • Additional compensation may include bonuses and equity.
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