Staff Digital Design Engineer
About The Position
As a Staff Digital Design Engineer on the Research & Development team at Infineon Technologies, you will contribute to the design and development of digital IP and SoCs. The role involves refining micro-architecture, implementing and documenting RTL, supporting integration, and preparing releases. You will develop reusable, configurable, integration-ready IP blocks and help translate IP and SoC roadmap requirements into design plans, deliverables, milestones, and risk-closure actions. You will drive design-quality closure through lint, CDC, RDC, synthesis, DFT checks, ATPG readiness, and other sign-off activities. You will debug issues across block, integration, and system levels in collaboration with Verification, Architecture, Physical Design, and System teams. The role also supports Automotive Base-T1 Ethernet PHY development and integration, promotes automated generator-based RTL flows, and contributes to IP architecture and design trade-off discussions.
Requirements
- Bachelor's or Master's degree in Electrical, Electronics, or Computer Engineering, or a related field.
- At least 3 years of hands-on experience in semiconductor digital IP design and RTL development.
- Solid SystemVerilog/Verilog RTL coding skills and a strong grasp of digital design fundamentals, including FSMs, clock domain crossing, and timing.
- Experience with micro-architecture definition, design documentation, integration support, and RTL release execution.
- Working knowledge of front-end design flows, including lint, CDC, and synthesis.
- Experience with verification and debug activities, including analyzing simulation failures and working with verification teams.
- Understanding of the chip development process.
Nice To Haves
- Knowledge of Ethernet protocols or experience with networking IC development.
- Scripting experience with Python, Tcl, or Perl, or exposure to generator-based RTL flows.
- Familiarity with automotive standards such as ISO 26262 functional safety.
Responsibilities
- Execute hands-on digital IP and SoC design, including micro-architecture refinement, RTL implementation, design documentation, integration support, and release readiness.
- Develop high-quality, synthesizable SystemVerilog/Verilog RTL for reusable, configurable, integration-ready IP blocks.
- Translate IP and SoC roadmap requirements into design plans, RTL deliverables, milestones, risks, and closure actions.
- Drive design-quality closure through lint, CDC, RDC, synthesis, DFT checks, ATPG readiness, and related sign-off activities.
- Debug and resolve design issues at block, integration, and system levels in collaboration with Verification, Architecture, Physical Design, and System teams.
- Support development and integration of Automotive Base-T1 Ethernet PHYs.
- Use automated, configurable, generator-based RTL flows to improve reuse, scalability, consistency, and productivity.
- Contribute to IP architecture and design trade-off discussions.
Benefits
- Eligibility to participate in an incentive plan.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
