Staff Engineer, ASIC Digital Design

Micron Technology•Minneapolis, MN
•$150,000 - $256,000

About The Position

As a Staff Digital Design Engineer on Micron’s ASIC logic design team, you will contribute to the design of next-generation internally developed ASICs and controller IP. You will translate architectural and product requirements into microarchitecture specifications and hardware implementations, and develop digital designs that interface with custom analog designs, third-party IP, and SystemVerilog blocks. The role covers RTL development for DRAM, NAND, and SSD controllers and systems, with attention to performance, power, area, timing, and testability. You will support the ASIC development flow from simulation, synthesis, timing closure, and formal verification through gate-level validation and silicon bring-up. The position also includes lab validation, HDL modeling, collaboration across engineering teams, and technical leadership through design reviews, mentoring, problem solving, and engineering best practices.

Requirements

  • B.S., M.S., or Ph.D. in Electrical Engineering.
  • At least 8 years of industry experience.
  • Strong fundamentals in logic design coding in SystemVerilog, verification techniques, and high-speed I/O crossings.
  • Strong written and verbal communication skills, including the ability to write and review architectural specifications and code.
  • Experience with software programming and tools such as Linux shell scripting and Python.
  • Understanding of analog and mixed-signal circuits and simulation, including CMOS/CML logic, PLL, DLL, and CDR.
  • Experience with DRAM interfaces, memory-system RAS (Reliability, Availability, Serviceability), and RTL development.
  • Experience with industry-standard tools related to synthesis, linting, equivalency, and formal verification.
  • Willingness to learn and use AI tools in the ASIC design flow.
  • Collaborative, curious, and motivated to contribute, learn, and grow.

Nice To Haves

  • Knowledge of Generative AI in the ASIC design flow.

Responsibilities

  • Translate architectural and product requirements into detailed microarchitecture specifications and robust hardware implementations.
  • Lead development of digital designs that interface with internally developed full-custom analog designs, third-party IP, and SystemVerilog blocks.
  • Design and develop RTL for next-generation DRAM, NAND, and SSD controllers and systems.
  • Own and support RTL development, simulation, synthesis, timing closure, formal verification, gate-level validation, and silicon bring-up support.
  • Partner with Design Verification, Analog Design, Synthesis, and Physical Design teams.
  • Participate hands-on in chip bring-up and lab validation.
  • Develop HDL models of circuits.
  • Provide technical leadership through design reviews, mentoring, problem solving, and development of engineering best practices.

Benefits

  • Medical, dental, and vision plans.
  • Programs to protect income in the event of illness or injury.
  • Paid family leave.
  • Paid time off.
  • Paid holidays.
  • Additional compensation may include bonuses and equity.
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