Staff Digital IC Design Engineer

MaxLinear • Irvine, CA

8d

About The Position

MaxLinear is seeking a Staff Digital IC Design Engineer to work on high-speed signal-processing, digital datapath, control, and interface functions. The role covers digital IC design from micro-architecture definition and RTL implementation through block-level verification, preliminary synthesis and power estimation, design checks, and support for post-silicon bring-up and debugging. The engineer will automate design tasks and collaborate with systems, communications systems, RFIC, and software teams.

Requirements

• Strong fundamentals in digital design, including fixed-point arithmetic, digital datapath design, finite-state machines, and area, power, and timing optimization.
• Experience with industry ASIC front-end design flow, including RTL coding, debugging, verification, synthesis, and support for timing closure.
• Experience with SoC integration, including clock/reset architecture, bus protocols, and serial interfaces.
• Strong logical and creative problem-solving abilities, with excellent analytical and debugging skills.
• Self-motivated, able to work effectively under pressure, and able to excel in a team environment.
• Able to ramp quickly on new technologies, products, and methodologies.
• Solid written and verbal communication skills.
• Bachelor's degree in Electrical Engineering or a related field and 5+ years of experience, or a master's degree and 3+ years of experience, or a Ph.D.

Nice To Haves

• Knowledge of communications/DSP algorithms and efficient ASIC implementations.

Responsibilities

• Define micro-architecture for high-speed signal processing, digital datapath, control, and interface functions.
• Implement protocol- or standards-compliant digital functions in SystemVerilog or Verilog RTL.
• Perform block-level verification, including creating testbenches and test plans, creating and debugging test cases, running RTL and gate-level simulations, and analyzing code coverage.
• Perform preliminary block-level synthesis and power estimation, including specifying SDC constraints and conducting vector-driven power analysis.
• Perform block-level design checks, including lint, CDC, and DFT-readiness checks.
• Support post-silicon bring-up and debug silicon in the lab.
• Automate design tasks using Python, Perl, shell scripts, and AI.
• Collaborate with systems, communications systems, RFIC, and software teams.

Benefits

• Health care benefits
• 401(k) savings plan
• Employee Stock Purchase Plan (ESPP)
• Paid time off
• Annual discretionary bonus eligibility
• Stock-based compensation for many positions

What This Job Offers

• Job Type: Full-time
• Career Level: Senior